DP83266VF National Semiconductor, DP83266VF Datasheet - Page 76

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DP83266VF

Manufacturer Part Number
DP83266VF
Description
IC MEDIA ACSS CTRL INTF 160PQFP
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83266VF

Applications
*
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
160-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interface
-
Other names
*DP83266VF
7 0 Control Information
7 5 2 Group Addresses
The Ring Engine supports detection of Group Addresses within programmable and fixed blocks of consecutive addresses The
algorithm used by the Ring Engine first performs a comparison between the most significant bits of the received DA with
programmable and fixed addresses If the most significant bits match the remaining bits are used as an index into a programma-
ble bit map If the indexed bit is 1 the A Flag is set to 1 if the indexed bit is 0 the A Flag remains 0
One programmable block of 256 group addresses is supported for group long addresses (GLA) and one programmable block of
group addresses is supported for group short addresses (GSA) Both of the programmable ranges share the same programma-
ble group address map (PGM)
For short addresses the first byte of a received DA is compared with GSA0 (bits GSA(15– 8)) If they match then the second
byte is used as an index into the PGM For long addresses the first 5 bytes of a received DA are compared with GLA0 through
GLA4 (bits GLA(47 –8)) If all 5 of these bytes match the corresponding byte in the received DA then the 6th byte of the
received DA is used as an index into the PGM The last byte of the address is used as an index into the PGM in both long and
short group addressing
A fixed block of 16 group addresses is supported for both long and short addresses at the end of the address space that
includes the Universal Broadcast address (FF
the last 4 bits are used as an index into the 16-bit Fixed Group Map (FGM) Similarly for long addresses if the first 44 bits are all
1’s the last 4 bits are also used as an index into the 16-bit FGM
The Group Addresses should be valid for at least 12 byte times before the Addressing Mode is enabled and should remain valid
for at least 12 byte times after the Addressing Mode is disabled in order to guarantee proper detection
Bits ELA (Enable Long Addressing) and ESA (Enable Short Addressing) in the Option Register determine the address types that
will be recognized by this MAC
Alternative group addressing schemes may be implemented using external matching logic that monitors the byte stream at the
PHY Interface The result of the comparison is returned using the EA (External A Flag) input signal
Group Long Address (GLA0–GLA4)
Group Long Address (GLA0–GLA4) represents the first 5 bytes of the long address bit GLA(47) to bit GLA(8)
To disable Long Group Address matches bits GLA(46–8) should be set to all One’s
Access Rules
Register Bits
Note GLA(47) should always be set to One
Group Short Address (GSA0)
Group Short Address (GSA0) represents the station’s short 16-bit address bit GSA(15) to bit GSA(8)
It is possible to disable Short Group Addressing by programming bits GSA(14– 8) to all Ones
Access Rules
Register Bits
Note GSA(15) is not used in the comparison since the comparison will only be accomplished if the received DA(15) is a One
GLA0
GLA1
GLA2
GLA3
GLA4
GSA0
048–04Ch
Address
Address
04Eh
GLA(47)
GLA(39)
GLA(31)
GLA(23)
GLA(15)
GSA(15)
D7
D7
Stop Mode
Stop Mode
Read
Read
GLA(46)
GLA(38)
GLA(30)
GLA(22)
GLA(14)
GSA(14)
D6
D6
Stop Mode
Stop Mode
Write
Write
GLA(45)
GLA(37)
GLA(29)
GLA(21)
GLA(13)
GSA(13)
D5
D5
(Continued)
GLA(44)
GLA(36)
GLA(28)
GLA(20)
GLA(12)
GSA(12)
D4
D4
FF) For short addresses if the first 12 bits of the received DA are all 1’s then
GLA(43)
GLA(35)
GLA(27)
GLA(19)
GLA(11)
GSA(11)
D3
D3
76
GLA(42)
GLA(34)
GLA(26)
GLA(18)
GLA(10)
GSA(10)
D2
D2
GLA(41)
GLA(33)
GLA(25)
GLA(17)
GLA(9)
GSA(9)
D1
D1
GLA(40)
GLA(32)
GLA(24)
GLA(16)
GSA(8)
GLA(8)
D0
D0

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