DP83266VF National Semiconductor, DP83266VF Datasheet - Page 96

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

D7 –D4
7 0 Control Information
Service Attention Register (SAR)
The Service Attention Register (SAR) is used to present the attentions for the service functions Each bit may be enabled by
setting the corresponding bit in the State Notify Register
This register is set to the value 0Fh upon reset
Access Rules
Register Bits
Bit
D0
D1
D2
D3
RES
D7
Address
108h
Symbol
PTOP
LMOP
ABR1
ABR0
RES
RES
D6
Pointer RAM Operation This bit is cleared by the host to cause the MACSI device to transfer data
between a Pointer RAM Register and a predefined mailbox location in memory The Pointer RAM Control
and Address Register contains the Pointer RAM Register address and determines the direction of the
transfer (read or write) The memory address is defined via the Mailbox Address Register This bit is set by
the MACSI device after it performs the data transfer
While PTOP
Address Register
Limit RAM Operation This bit is cleared by the host to cause the MACSI device to transfer data between
a Limit RAM Register and the Limit Data and Limit Address Registers The Limit Address Register
contains the Limit RAM Register address and determines the direction of the transfer (read and write)
This bit is set by the MACSI device after it performs the data transfer
While LMOP
Abort Request RCHN1 This bit is cleared by the host to abort a Request on RCHN1 This bit is set by the
MACSI device when RQABORT ends a request on RCHN1 The host may write a 1 to this bit which may
or may not prevent the request from being aborted When this bit is cleared by the host the USR1 bit in
the Request Attention Register is set and further processing on RCHN1 is halted
Abort Request RCHN0 This bit is cleared by the host to abort a Request on RCHN0 This bit is set by the
MACSI device when RQABORT ends a request on RCHN0 The host may write a 1 to this bit which may
or may not prevent the request from being aborted When this bit is cleared by the host the USR0 bit in
the Request Attention Register is set and further processing on RCHN0 is halted
Reserved
Always
Read
RES
D5
e
e
0 the host must not alter the Pointer RAM Address and Control Register or the Mailbox
0 the host must not alter either the Limit Address or Limit Data Register
(Continued)
RES
D4
Conditional
Write
ABR0
D3
96
ABR1
D2
Description
LMOP
D1
PTOP
D0