OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 4

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
3. Functional problems detail
ES_LPC122X
Errata sheet
3.1 ADC.1: PIO0_2, PIO1_5 trigger sources to ADC do not operate
3.2 RTC.1: RTC Wake up from Deep-sleep requires use of WDOsc
properly
Introduction:
There are two asynchronous trigger inputs to the analog to digital converter: PIO0_2 and
PIO1_5, There are also four timer driven synchronous trigger sources controlled by timer
MAT events.
Problem:
Asynchronous trigger events on PIO0_2 and PIO1_5 can be lost by the analog to digital
converter. Synchronous sources are unaffected and can be used without issue.
Work-around:
None.
Introduction:
The LPC122x features the ability to wake up from Deep-sleep mode in a self timed
manner using the lower power Real Time Clock (RTC). Once RTC is powered and the
clock source is configured, a match event will generate an interrupt and wake the
LPC122x.
Problem:
In order to wake from Deep-sleep via RTC, the system must be clocked by the WDOsc
while in Deep-Sleep.
Work-around:
Prior to entering Deep-sleep the WDOsc must be powered, and the main clock source
selection register must source the main clock with the WDOsc. The WDOsc must be
configured to use the lowest operating frequency by selecting the 0.5 MHz input
(FREQSEL) and post divide value of 64 (DIVSEL). The Deep-sleep mode configuration
register must be written with values corresponding to the "WD oscillator on" column in
Table 44 of the User Manual. Refer to the section "Deep-sleep mode" in the Power
Management section of the System Control chapter of the User Manual for additional
details and restrictions on Deep-sleep.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 May 2011
Errata sheet LPC1224/25/26/27
ES_LPC122x
© NXP B.V. 2011. All rights reserved.
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