TS68C429AMFA E2V, TS68C429AMFA Datasheet - Page 19

• Manufacturer Part Number: TS68C429AMFA
• Manufacturer: E2V

Specifications of TS68C429AMFA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / Rohs Status: Compliant

Table 8-1.
e2v semiconductors SAS 2008
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 0 to 3
Register Control Register Description (Continued)
Function
Wrong parity: this feature is
enabled only if the self-test
register bit 0 is set 1
Not used
Not used
Not used
Channel priority: order
•
The gap register is accessible for writing operations only. It contains the value on which the gap counter
will be stopped and will generate the end of the message signal (see
interpreted as a multiple of the CLK ARINC period.
Figure 8-5.
The value of the gap register must be chosen so as to generate the end of the message before the mini-
mal gap as defined in the ARINC-429 norm.
•
The Buffer is made of two 16-bit registers, the Most Significant Word of the message (MSW) is contained
in the lower address register, the Least Significant Word of the message (LSW) is contained in the upper
address register. For correct behavior, the MSW must be read before the LSW. They are accessible in
read mode only and 16-bit access is mandatory.
•
The label control matrix is a 256 x 1 bit memory. There is one memory per channel.
The address is driven by the incoming label, the output data is used to validate this incoming message
label (see
receiver-control-register should be set to “1” to allow the access. At this time, the address is driven by the
external address bus and the data are written from the data bus D7 to D0 (one per channel according to
Figure
trol matrix can be written or read in byte and word mode. In word mode, the state of D15-D8 is unknown.
After complete programming of the matrix, the LCMWE bit should be reset to “0” to allow normal receiv-
ing mode. A “1” in the memory means that this label is allowed and a “0” means that this label must be
ignored.
Gap Register
Message Buffer
Label Control Matrix
8-7). Any write to a matrix on which the LCMWE is not set will not have any effect. The label con-
Figure
Gap Register Description
(Figure
8-6). To program this matrix, the LCMWE (label control matrix write enable) bit of the
8-5)
Comments
0: received message parity is correct if read, reset wrong parity flag if written.
1: an incorrect received message parity has been detected (the corresponding
message is lost) (set by hardware).
The lowest value will give the highest priority. Each channel must have a unique
channel priority order.
If several messages are pending, the interrupt vector will account for highest priority
channel.
“Inputs” on page
0848E–HIREL–02/08
TS68C429A
14). The value is
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