TS68C429AMFA E2V, TS68C429AMFA Datasheet - Page 29

• Manufacturer Part Number: TS68C429AMFA
• Manufacturer: E2V

Specifications of TS68C429AMFA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / Rohs Status: Compliant

e2v semiconductors SAS 2008
•
Any internal status change that induces a bit to be set in the status-register will generate an interrupt if
this cause is enabled by the Mask-register and if no highest priority cause is already activated or
pending.
For the receiver blocks, the priority is programmable (see interrupt vector number description). For the
transmitter block, the End-of-transmission has higher priority than FIFO-empty and channel 1 has higher
priority than channel 2 that has higher priority than channel 3.
The RX wrong parity bit can be set only if self-test register bit 0 is set to 1.
The user has to check which receiver has it receiver control register bit 7 set to 1.
At the end of the interrupt procedure, the user must reset RX wrong parity bit to 0.
RX wrong parity is the highest interrupt priority source for the receiver part of the MRT.
•
The mask register is accessible for reading and writing operations. The mask register is used to disable
interrupt source. The bit order is the same as in the status register. A “0” indicates that this source is dis-
able, a “1” enables an interrupt for this source.
Figure 9-10. Mask Register
•
The base register is only accessible for writing operations by the user. The base register must be pro-
grammed at the initialization phase. It contains the base for the vector generation during an interrupt
acknowledge. This allows the use of several peripherals. If not programmed interrupt vector is set to
$OF.
Register Description
The Mask Register
The Base Register
0848E–HIREL–02/08
TS68C429A
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