P87C51X2BBD NXP Semiconductors, P87C51X2BBD Datasheet - Page 18
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P87C51X2BBD
Manufacturer Part Number
P87C51X2BBD
Description
MCU 8-Bit 87C 80C51 CISC 4KB EPROM 5V 44-Pin LQFP Tray
Manufacturer
NXP Semiconductors
Datasheet
1.P87C52X2BN112.pdf
(62 pages)
Specifications of P87C51X2BBD
Package
44LQFP
Device Core
80C51
Family Name
87C
Maximum Speed
33 MHz
Ram Size
128 Byte
Program Memory Size
4 KB
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
32
Interface Type
UART
Operating Temperature
0 to 70 °C
Number Of Timers
3
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Philips Semiconductors
Table 4. Timer 2 Operating Modes
2003 Jan 24
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
T2CON
RCLK + TCLK
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
X
0
0
1
Bit Addressable
Address = C8H
Position
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
TF2
7
Name and Significance
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select. (Timer 2)
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
CP/RL2
X
X
0
1
EXF2
6
0 = Internal timer (OSC/12 in 12-clock mode or OSC/6 in 6-clock mode)
1 = External event counter (falling edge triggered).
Figure 6. Timer/Counter 2 (T2CON) Control Register
RCLK
5
TCLK
TR2
4
1
1
1
0
18
EXEN2
3
16-bit Auto-reload
16-bit Capture
Baud rate generator
(off)
TR2
2
C/T2
1
P80C3xX2; P80C5xX2;
Reset Value = 00H
MODE
CP/RL2
0
P87C5xX2
SU01621
Product data