P87LPC767BN NXP Semiconductors, P87LPC767BN Datasheet - Page 15

• Manufacturer Part Number: P87LPC767BN
• Description: MCU 8-Bit 87LP 80C51 CISC 4KB EPROM 3.3V/5V 20-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC767BN

• Package: 20PDIP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 18
• Interface Type: I2C/UART
• On-chip Adc: 4-chx8-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
Analog Comparators
Two analog comparators are provided on the P87LPC767. Input and
output options allow use of the comparators in a number of different
configurations. Comparator operation is such that the output is a
logical one (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than
the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be
configured to cause an interrupt when the output value changes.
Comparator Configuration
Each comparator has a control register, CMP1 for comparator 1 and
CMP2 for comparator 2. The control registers are identical and are
shown in Figure 4.
2002 Mar 25
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
CMPn
BIT
CMPn.7, 6
CMPn.5
CMPn.4
CMPn.3
CMPn.2
CMPn.1
CMPn.0
Address: ACh for CMP1, ADh for CMP2
Not Bit Addressable
SYMBOL
CMFn
CEn
CPn
CNn
OEn
COn
—
—
7
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Comparator enable. When set by software, the corresponding comparator function is enabled.
Comparator output is stable 10 microseconds after CEn is first set.
Comparator positive input select. When 0, CINnA is selected as the positive comparator input. When
1, CINnB is selected as the positive comparator input.
Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as
the negative comparator input. When 1, the internal comparator reference V
negative comparator input.
Output enable. When 1, the comparator output is connected to the CMPn pin if the comparator is
enabled (CEn = 1). This output is asynchronous to the CPU clock.
Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the
comparator is disabled (CEn = 0).
Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes
state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by
software and when the comparator is disabled (CEn = 0).
Figure 4. Comparator Control Registers (CMP1 and CMP2)
—
6
CEn
5
CPn
4
12
CNn
3
The overall connections to both comparators are shown in Figure 5.
There are eight possible configurations for each comparator, as
determined by the control bits in the corresponding CMPn register:
CPn, CNn, and OEn. These configurations are shown in Figure 6.
The comparators function down to a V
When each comparator is first enabled, the comparator output and
interrupt flag are not guaranteed to be stable for 10 microseconds.
The corresponding comparator interrupt should not be enabled
during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate
interrupt service.
OEn
2
COn
1
CMFn
0
ref
DD
Reset Value: 00h
is selected as the
of 3.0 V.
P87LPC767
SU01152
Product data