M25P128-VMF6PB Micron Technology Inc, M25P128-VMF6PB Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
M25P128-VMF6PB
Manufacturer Part Number
M25P128-VMF6PB
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25P128-VMF6PB.pdf
(47 pages)
Specifications of M25P128-VMF6PB
Cell Type
NOR
Density
128Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SO W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
16M
Supply Current
8mA
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P128-VMF6PB
Manufacturer:
CIRRUS
Quantity:
320
Part Number:
M25P128-VMF6PB
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P128-VMF6PB,M25P128-VMF6TP
Quantity:
70
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/V
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/V
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W/V
If Write Protect (W/V
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write status register (WRSR) instruction sequence
If Write Protect (W/V
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/V
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/V
or by driving Write Protect (W/V
(SRWD) bit.
PP
S
C
D
Q
) Low
PP
) High.
PP
) is permanently tied High, the Hardware Protected Mode (HPM) can
0
PP
PP
1
) is driven High, it is possible to write to the Status Register
) is driven Low, it is not possible to write to the Status Register
High Impedance
2
Instruction
3
PP
4
) is driven High or Low.
PP
5
) Low after setting the Status Register Write Disable
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
AI02282D
PP
):
25/47