M25P128-VMF6PB Micron Technology Inc, M25P128-VMF6PB Datasheet - Page 28
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M25P128-VMF6PB
Manufacturer Part Number
M25P128-VMF6PB
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25P128-VMF6PB.pdf
(47 pages)
Specifications of M25P128-VMF6PB
Cell Type
NOR
Density
128Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SO W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
16M
Supply Current
8mA
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P128-VMF6PB
Manufacturer:
CIRRUS
Quantity:
320
Part Number:
M25P128-VMF6PB
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P128-VMF6PB,M25P128-VMF6TP
Quantity:
70
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Page program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence. The instruction sequence is
shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see
characteristics for 65 nm devices
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see
Figure
PP
) is initiated. While the Page Program cycle is in progress, the Status Register
15.
Table 2
and
and
Table 17: AC characteristics for 130 nm
Table
3) is not executed.
Table 15: AC
devices).