74LV4051D,118 NXP Semiconductors, 74LV4051D,118 Datasheet - Page 4
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74LV4051D,118
Manufacturer Part Number
74LV4051D,118
Description
IC MUX/DEMUX 8X1 16SOIC
Manufacturer
NXP Semiconductors
Series
74LVr
Type
Analog Multiplexerr
Datasheet
1.74LV4051PW118.pdf
(26 pages)
Specifications of 74LV4051D,118
Package / Case
16-SOIC (0.154", 3.90mm Width)
Function
Multiplexer/Demultiplexer
Circuit
1 x 8:1
On-state Resistance
60 Ohm
Current - Supply
80µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Propagation Delay Time
23 ns
Supply Voltage (max)
6 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package
16SO
Maximum On Resistance
375@2V Ohm
Maximum Propagation Delay Bus To Bus
25(Typ)@1.2V|9(Typ)@2V|6(Typ)@2.7V|5(Typ)@3.3V|4(Typ)@4.5V|3(Typ)@6V ns
Maximum High Level Output Current
25 mA
Multiplexer Architecture
8:1
Maximum Turn-on Time
145(Typ)@1.2V ns
Power Supply Type
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LV4051D-T
74LV4051D-T
935190970118
74LV4051D-T
935190970118
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LV4051D,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
5. Pinning information
Table 2.
74LV4051_4
Product data sheet
Symbol
E
V
GND
S0, S1, S2
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output
Z
V
Fig 5.
EE
CC
GND
V
Y4
Y6
Y7
Y5
EE
E
Z
Pin configuration SOT38-4
and SOT109-1
Pin description
1
2
3
4
5
6
7
8
74LV4051
5.1 Pinning
5.2 Pin description
001aak433
16
15
14
13
12
11
10
9
V
Y2
Y1
Y0
Y3
S0
S1
S2
CC
Pin
6
7
8
11, 10, 9
3
16
Fig 6.
GND
V
Y4
Y6
Y7
Y5
EE
E
Z
1
2
3
4
5
6
7
8
Rev. 04 — 10 August 2009
Pin configuration
SOT338-1 and SOT403-1
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
common output or input
supply voltage
74LV4051
001aak407
8-channel analog multiplexer/demultiplexer
16
15
14
13
12
11
10
9
V
Y2
Y1
Y0
Y3
S0
S1
S2
CC
Fig 7.
index area
terminal 1
V
Y6
Y7
Y5
EE
Pin configuration for
SOT763-1
E
Z
Transparent top view
2
3
4
5
6
7
74LV4051
74LV4051
V
CC
© NXP B.V. 2009. All rights reserved.
(1)
15
14
13
12
11
10
001aak408
Y2
Y1
Y0
Y3
S0
S1
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