JSH-42L3AD3-20 JDS UNIPHASE, JSH-42L3AD3-20 Datasheet - Page 37

• Manufacturer Part Number: JSH-42L3AD3-20
• Manufacturer: JDS UNIPHASE

Specifications of JSH-42L3AD3-20

• Number Of Receivers: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature (max): 85C
• Lead Free Status / Rohs Status: Compliant

Vendor Specific Digital Diagnostic Monitor TX_FAULT Alarm/Warning Interrupt
The transceiver has the ability to be programmed to indicate TX_FAULT when one of the five DDM signals
goes outside an alarm or warning threshold. This allows the customer the option of using the TX_FAULT as
an interrupt instead of constantly polling the diagnostic signals. The TX_FAULT Alarm/Warning interrupt con-
trol bytes are accessible as one of the selectable tables in the Vendor specific area at offset 248-255.
To enable the TX_FAULT as an Alarm/Warning, use the following procedure:
This alarm/warning interrupt enable/latch space will be volatile across power-cycles and resets. This space
can be accessed sequentially and contiguously within the offsets defined for it. If during the course of a
sequential, multi-byte write, the offset being written reaches the end of this vendor specific area, the next byte
of data that will be attempted to be written will be at offset 0.
The Alarm/Warning Interrupt Enable bits are written by the host. They are used by the transceiver to generate
a TX_FAULT signal usable as an interrupt to the host for an alarm/warning condition. The general definition
of the function is that when the host sets an Interrupt Enable bit (offsets 248-251) for an Alarm/Warning to
0b1, then the corresponding Alarm/Warning Latch bit (offsets 252-255) will be latched to 0b1 when the corre-
sponding Alarm/Warning bit (Alarm bits at offsets 112-113 and Warning bits at offsets 116-117) becomes
active. The Alarm/Warning Latch bit will remain 0b1 until the host clears the Latch bit by writing a 0b1 to it, at
which time the transceiver will re-process the Latch bit. While any of the Alarm/Warning Latch bits are a 0b1,
the transceiver will set the TX_FAULT signal active.
Note: When used in the Alarm/Warning Interrupt mode, the TX_FAULT signal does not necessarily indicate
that the transceiver is not transmitting. When TX_FAULT becomes active, the host should disable all
Alarm/Warning Interrupt Enable bits and clear all Alarm/Warning Latch bits In order to determine whether
there is a hardware TX_FAULT that does indicate hardware transmission loss.
Monitor Data Table 9 Alarm/Warning Enables and Latches
October 2008
Address
Byte
248
248
248
248
248
248
248
248
249
249
249
250
5-0
Bit
7
6
5
4
3
2
1
0
7
6
7
Temp High Alarm Interrupt Enable
Temp Low Alarm Interrupt Enable
Voltage High Alarm Interrupt Enable
Voltage Low Alarm Interrupt Enable
TX Bias High Alarm Interrupt Enable
TX Bias Low Alarm Interrupt Enable
TX Power High Alarm Interrupt Enable
TX Power Low Alarm Interrupt Enable
RX Power High Alarm Interrupt Enable
RX Power Low Alarm Interrupt Enable
Reserved
Temp High Warning Interrupt Enable
Name
1
1
1
1
1
1
1
1
1
1
1
Enable bit for the temperature high alarm.
Enable bit for the temperature low alarm.
Enable bit for the voltage high alarm.
Enable bit for the voltage low alarm.
Enable bit for the laser current high alarm.
Enable bit for the laser current low alarm.
Enable bit for the fiber coupled power high alarm.
Enable bit for the fiber coupled power low alarm.
Enable bit for the received power high alarm.
Enable bit for the received power low alarm.
Reserved
Enable bit for the temperature high warning.
JSH-42L3AD3-20S / 64P0682
JDSU Product Specification 21121822-001
Description of Fields
LW 4x/2x/1x FC SFP with DDM
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