M25P64-VME6TG Micron Technology Inc, M25P64-VME6TG Datasheet - Page 27

• Manufacturer Part Number: M25P64-VME6TG
• Manufacturer: Micron Technology Inc

Specifications of M25P64-VME6TG

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFPN EP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

6.4.4
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/V
(W/V
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
PP
) signal allow the device to be put in the Hardware Protected mode (when the Status
PP
sequence
0
High Impedance
) signal. The Status Register Write Disable (SRWD) bit and Write Protect
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
Table
4
PP
3
) is driven Low). In
2) becomes
2
1
0
7
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