PPC440GX-3NF667C Applied Micro Circuits Corporation, PPC440GX-3NF667C Datasheet - Page 13

• Manufacturer Part Number: PPC440GX-3NF667C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF667C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

Revision 1.20 – June 9, 2009
Serial Port
Features include:
IIC Bus Interface
Features include:
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
General Purpose IO (GPIO) Controller
AMCC
• Support for peripherals running on slower frequency buses
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
• Two IIC interfaces provided
• Support for Philips® Semiconductors I
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• 32-bit Time Base Counter driven by the OPB bus clock
• Seven 32-bit compare timers
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
Data Sheet
accesses.
capabilities acts as a GPIO or is used for another purpose.
tri-stated if output bit is 1).
DD
IIC interface
2
C Specification, dated 1995
440GX – Power PC 440GX Embedded Processor
13