PPC440EPX-SUA667T Applied Micro Circuits Corporation, PPC440EPX-SUA667T Datasheet
PPC440EPX-SUA667T
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PPC440EPX-SUA667T Summary of contents
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... NAND Flash on the NAND Flash interface. • Optional security feature (PPC440EPx-S). • Available in RoHS compliant, lead-free package. (PPC440EPx-S), and general purpose I/O. Technology: CMOS Cu-11, 0.13μm. Package: 35mm, 680-ball thermally enhanced plastic ball grid array (TE-EPBGA). RoHS compliant package available ...
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... PPC440EPx Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Floating Point Unit (FPU SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Security Function (optional KASUMI Algorithm (optional PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External Peripheral Bus Controller (EBC Ethernet Controller ...
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... Revision 1.30 – February 27, 2009 Data Sheet Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC440EPx Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 35mm, 680-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 5. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 6. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 7. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 8 ...
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... AMCC Part Number Security Feature Package Note: The example P/N above contains the security feature, is lead-free and is capable of running at 667MHz. 4 Revision Package 35mm, 680 TE-EPBGA 35mm, 680 TE-EPBGA PPC440EPx-SUA667T Revision 1.30 – February 27, 2009 Data Sheet PVR Value JTAG ID Level A 0x216218D0 0x0440F1E1 ...
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... The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus Address Maps The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs) ...
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... PPC440EPx Embedded Processor Table 1. System Memory Address Map (Sheet Function Total System Memory Address Space Local Memory USB 2.0 Device USB 2.0 Host On-Chip Memory Security (PPC440EPx-S) 1 PCI 1 EBC 1 PCI 6 Sub Function Start Address 0 0000 0000 DDR SDRAM 0 0000 0000 ...
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... Function Internal Peripherals 1 EBC Boot space Notes: 1. EBC and PCI are relocatable, but this map reflects the suggested configuration. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Sub Function Start Address Reserved 1 EF50 0000 General Purpose Timer 1 EF60 0000 Reserved 1 EF60 0200 ...
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... PPC440EPx Embedded Processor Table 2. DCR Address Map (Sheet Function 1 Total DCR Address Space By function: Reserved Clocking Power On Reset (CPR0) System DCRs (SDR0) Memory Controller (SDRAM0) External Bus Controller (EBC0) Reserved PLB4-to-PLB3 Bridge PLB3-to-PLB4 Bridge Reserved PLB3 Arbiter PLB4 Arbiter ...
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... On Chip Memory (SRAM Controller) Reserved Notes: 1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 B). AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Start Address End Address 380 38F 390 ...
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... PPC440EPx Embedded Processor PowerPC 440 Processor The PowerPC 440 processor is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. ...
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... DCR – 32-bit data path – 10-bit address Security Function (optional) The built-in security function (PPC440EPx-S only cryptographic engine attached to the 128-bit PLB with built- in DMA and interrupt controllers. Features include: • Federal Information Processing Standard (FIPS) 140-2 design • Support for an unlimited number of Security Associations (SA) • ...
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... PPC440EPx Embedded Processor • Secure Socket Layer (SSL) and Transport Layer Security (TLS) features – Packet transforms – One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher • Secure Real-Time Protocol (sRTP) features – Packet transforms – ...
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... Burst Wait States for first access and Wait States for subsequent accesses – Programmable CSon, CSoff relative to address – Programmable OEon, WEon, WEoff ( clock cycles) relative to CS • Programmable address mapping • External DMA Slave Support AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 13 ...
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... Allows external master access to all non-EBC PLB slaves – External master can control EBC slaves for access Ethernet Controller Ethernet support provided by the PPC440EPx interfaces to the physical layer but the PHY is not included on the chip: • Two 10/100/1000 interfaces running in full- and half-duplex modes providing: – ...
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... The USB 2.0 interface provides both device and host support. One interface provides host or device support and operates through an internal PHY. The other interface provides device support only through the UTMI interface with no internal PHY. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 2 C Specification, dated 1995 15 ...
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... PPC440EPx Embedded Processor Features include: • USB 2.0 Host with internal PHY – Fully compliant to the following specifications: • Universal Serial Bus Specification, Revision 2.0. • Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 2.0. • Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a. ...
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... Programmable critical interrupt vector for faster vector processing JTAG Features include: • IEEE 1149.1 Test Access Port • JTAG Boundary Scan Description Language (BSDL) • Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with this port. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor 17 ...
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... PPC440EPx Embedded Processor Package Diagram Figure 3. 35mm, 680-Ball TE-PBGA Package Top View 30 24 TYP TYP Side View Mold Compound 2.65 max Bottom View 35.0 ± 0.20 33 Thermal Balls Part Number Heat Slug PCB Substrate 0.4 - 0.6 1.0 Notes: 9.0 ...
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... Time within 5°C of Actual Peak Temperature Ramp-down Rate Time 25°C to Peak Temperature Table 4. JEDEC Moisture Sensitivity Level and Ball Composition MSL Level Solder Ball Metallurgy AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Sn-Pb Eutectic Assembly 3°C/Second Max 100°C 150°C 60-120 Seconds 183°C 60-150 Seconds 225 +0/-5° ...
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... PPC440EPx Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list— ...
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... DD EOV DD EOV DD EOV DD EOV DD EOV DD EOV DD EOV DD EOV DD EOV DD [ExtAck][USB2XcvrSel]GPIO30 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AM21 AM19 AL16 AM13 AE03 DDR SDRAM AB04 W04 U04 AP10 R02 System E32 AP27 Power AP28 AM11 AL11 AM09 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 3 of 25) Signal Name [ExtReq][USB2RxErr]GPIO27 ExtReset GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk, SMIIRefClk GMCRxClk, GMC0RxClk, SMIISync GMCRxD0, GMC0RxD0, SMII0RxD GMCRxD1, GMC0RxD1, SMII1RxD GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4, GMC1RxD0 ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group A01 A02 A03 A28 A32 A33 A34 B01 B02 B03 B04 B08 B16 B19 B26 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 5 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group R22 T02 T05 T15 T16 T17 T18 T19 T20 T30 T33 U05 U13 U14 U15 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 7 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AK05 AK08 AK10 AK16 AK17 AK19 AK25 AK27 AK30 AK31 AL03 AL04 AL05 AL06 AL29 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 9 of 25) Signal Name GND GND GND GND GND GND GND GPIO00[PerAddr07][DMAReq2] GPIO01[PerAddr06][DMAAck2] GPIO02[PerAddr05][EOT2/TC2] GPIO03[PerAddr04][DMAReq3] GPIO04[PerAddr03][DMAAck3] GPIO05[PerAddr02][EOT3/TC3] GPIO06[PerCS1][NFCE1] GPIO07[PerCS2][NFCE2] GPIO08[PerCS3][NFCE3] GPIO09[PerCS4] GPIO10[PerCS5] GPIO11[PerErr] ...
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... GPIO54[TrcES2] GPIO55[TrcES3] GPIO56[TrcES4] GPIO57[TrcTS0] GPIO58[TrcTS1] GPIO59[TrcTS2] GPIO60[TrcTS3] GPIO61[TrcTS4] GPIO62[TrcTS5] GPIO63[TrcTS6] Halt[DrvrInh2] [HoldAck][USB2Susp]GPIO29 [HoldPri]USB2LS1[LeakTest] [HoldReq]USB2RxAct[RcvrInh] IIC0SClk IIC0SData[GPIO26] AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group R03 R04 C28 C29 A29 B29 D28 B28 AD33 AC31 AD34 U34 V32 U33 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 11 of 25) Signal Name [IIC1SClk]SCPClkOut [IIC1SData]SCPDI [IRQ0]GPIO40 [IRQ1]GPIO41 [IRQ2]GPIO42 [IRQ3]GPIO43 [IRQ4]GPIO44[DMAAck1] IRQ5[ModeCtrl][DMAReq1] [IRQ6]GPIO45[EOT1/TC1] [IRQ7]GPIO46[DMAReq0] [IRQ8]GPIO47[DMAAck0] [IRQ9]GPIO48[EOT0/TC0] [LeakTest]USB2LS1[HoldPri] [LeakTest2]USB2RxDV MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 ...
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... MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group AN22 AP22 AM20 AL20 AL22 AM22 AN21 AP21 AP20 AL18 AN17 AP17 AN20 AP19 AN18 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 13 of 25) Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group B17 D10 B09 D09 D08 NAND Flash A18 A17 D17 A16 F06–F29 G06–G29 H06–H29 J06– ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 15 of 25) Signal Name No ball No ball No ball No ball No ball No ball No ball Revision 1.30 – February 27, 2009 Ball Interface Group AC06–AC29 AD06–AD29 AE06–AE29 A physical ball does not exist at these ball AF06– ...
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... PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 PCIC1/BE1 PCIC2/BE2 PCIC3/BE3 PCIClk PCIDevSel PCIFrame AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group D29 A30 C30 A31 D34 F31 E34 F32 F33 F34 G31 G33 G34 H31 H32 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 17 of 25) Signal Name PCIGnt0/Req PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY 36 Revision 1.30 – February 27, 2009 Ball Interface Group ...
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... PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0[NFCE0] [PerCS1][NFCE1]GPIO06 [PerCS2][NFCE2]GPIO07 [PerCS3][NFCE3]GPIO08 [PerCS4]GPIO09 [PerCS5]GPIO10 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group C26 D26 A26 D25 C25 B25 A25 C24 D24 B24 D23 A24 C23 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 19 of 25) Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16[USB2DO0] PerData17[USB2DO1] PerData18[USB2DO2] PerData19[USB2DO3] PerData20[USB2DO4] PerData21[USB2DO5] PerData22[USB2DO6] PerData23[USB2DO7] PerData24[USB2DI0] PerData25[USB2DI1] PerData26[USB2DI2] PerData27[USB2DI3] ...
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... DD SOV DD SV REF1A SV REF1B SV REF2A SV REF2B SysClk SysErr SysReset TCK TDI AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group A14 External Slave Peripheral A15 B15 External Slave Peripheral C15 D15 A20 System AJ04 DDR SDRAM D07 System B06 System ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 21 of 25) Signal Name TDO TestEn TherMonA TherMonB TmrClk TMS [TrcBS0]GPIO49 [TrcBS1]GPIO50 [TrcBS2]GPIO51 TrcClk [TrcES0]GPIO52 [TrcES1]GPIO53 [TrcES2]GPIO54 [TrcES3]GPIO55 [TrcES4]GPIO56 [TrcTS0]GPIO57 [TrcTS1]GPIO58 [TrcTS2]GPIO59 [TrcTS3]GPIO60 [TrcTS4]GPIO61 [TrcTS5]GPIO62 [TrcTS6]GPIO63 TRST [UART0_CTS/UART3_Rx]GPIO36[PerDataPar0] [UART0_DCD/UART1_CTS/UART2_Tx]GPIO34 [UART0_DSR/UART1_RTS/UART2_Rx]GPIO35 [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 ...
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... USB2LS0[DrvrInh1] USB2LS1[LeakTest][HoldPri] [USB2OM0]GPIO32[PerDataPar2] [USB2OM1]GPIO33[PerDataPar3] USB2RExt USB2RxAct[HoldReq][RcvrInh] USB2RxDV[LeakTest2] [USB2RxErr]GPIO27[ExtReq] [USB2Susp]GPIO29[HoldAck] [USB2TermSel]GPIO31[BusReq] USB2TxRdy[RefEn] [USB2TxVal]GPIO28 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group L01 L02 J04 L04 Power M01 M04 J03 K04 K01 A05 Universal Serial Bus F02 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 23 of 25) Signal Name [USB2XcvrSel]GPIO30[ExtAck] USB2Xcvr USB2Xcvr USB2XtalIn USB2XtalOut 42 Revision 1.30 – February 27, 2009 Ball Interface Group M03 Universal Serial Bus J02 Universal Serial Bus J01 N02 Universal Serial Bus N03 Data Sheet ...
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... AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Ball Interface Group E11 E12 E13 E14 E15 E20 E21 E22 E23 E24 L05 L30 M05 M30 N05 N16 N19 Power N30 P05 P16 P19 P30 R05 R30 T13 T14 T21 T22 W13 W14 ...
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... PPC440EPx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 25 of 25) Signal Name Signals in Ball Assignment Order In the following table, only the primary (default) signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what other signals or functions are on those balls, look up the primary signal name in Table 5 on page 20 ...
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... B29 A30 PCIAD01 B30 A31 PCIAD03 B31 A32 GND B32 A33 GND B33 A34 GND B34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name GND C01 PerData17* GND C02 GND GND C03 GND GND C04 GND OV C05 ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball E01 PerData21* F01 OV E02 F02 DD E03 PerData16* F03 E04 PerData19* F04 E05 GND F05 OV E06 F06 DD OV E07 F07 DD E08 GND F08 OV E09 F09 DD E10 GND ...
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... J29 No Ball K29 OV J30 K30 DD J31 PCIC1/BE1 K31 J32 PCIPar K32 J33 PCIPErr K33 J34 PCISErr K34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name U1AV U2AGND L01 DD U1AV TMS L02 DD TDI L03 USB2RExt U2AV U2AGND L04 DD V ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball N01 GND P01 N02 USB2XtalIn P02 N03 USB2XtalOut P03 N04 GND P04 V N05 P05 DD N06 No Ball P06 N07 No Ball P07 N08 No Ball P08 N09 No Ball P09 ...
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... V29 OV U30 V30 DD U31 PCIReq1 V31 U32 GPIO46* V32 U33 GPIO45* V33 U34 GPIO43* V34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name MemData61 W01 MemData55 MemData60 W02 GND MemData51 W03 MemData54 MemData50 W04 DQS6 SOV W05 ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AA01 MemData53 AB01 AA02 MemData52 AB02 AA03 MemData43 AB03 AA04 MemData42 AB04 V AA05 AB05 DD AA06 No Ball AB06 AA07 No Ball AB07 AA08 No Ball AB08 AA09 No Ball AB09 ...
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... AF29 AE30 GND AF30 AE31 GPIO52* AF31 AE32 GPIO50* AF32 AE33 GPIO51* AF33 AE34 GPIO49* AF34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name MemData33 AG01 MemODT1 MemData37 AG02 GND MemData32 AG03 MemData36 SV AG04 MemAddr13 REF2A SOV ...
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... PPC440EPx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AJ01 GND AK01 AJ02 WE AK02 AJ03 BA0 AK03 AJ04 RAS AK04 SOV AJ05 AK05 DD AJ06 No Ball AK06 AJ07 No Ball AK07 AJ08 No Ball AK08 AJ09 No Ball AK09 ...
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... EOV AN30 AP30 DD AN31 GND AP31 AN32 GND AP32 AN33 GND AP33 AN34 GND AP34 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Signal Name Ball Signal Name GND GND GND MemAddr01 MemAddr02 MemAddr04 MemAddr09 BA2 ECC7 DQS8 ECC4 MemData26 MemData24 MemData19 ...
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... In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address pins (PerAddr) are used as outputs by the PPC440EPx to broadcast an address to external slave devices when the PPC440EPx has control of the external bus. When, during normal operation, an external master gains ownership ...
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... Data Sheet of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440EPx. In this example, the pins are also bidirectional, serving both as inputs and outputs. Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown ...
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... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... DDR2 On-die termination enable (not used with DDR1). RAS Row Address Strobe. WE Write Enable. S DDR SDRAM reference voltage 1 input. VREF1A:B S DDR SDRAM reference voltage 2 input. VREF2A:B AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description Notes I/O Type 2 ...
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... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
Page 59
... PerCS1:5 External peripheral device select. Used by either peripheral controller or DMA controller depending PerOE upon the type of transfer involved. When the PPC440EPx is the bus master, it enables the selected device to drive the bus. PerReady Used by a peripheral slave to indicate it is ready to transfer data. ...
Page 60
... If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440EPx needs to regain BusReq control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440EPx to indicate ExtAck that a data transfer occurred ...
Page 61
... Indicates status of device during program erase or page read. This signal is wire-OR connected from all NAND Flash devices. Read Enable. NFREn Data is latched on the rising edge. Write Enable. NFWEn Data is latched on the rising edge. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet ...
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... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
Page 63
... On-chip PNP thermal monitor transistor. TherMonA the emitter and B is the base. The collector is grounded. Module characterization and screening. Use for test purposes PSROOut only. Tie down as specified in Note 3 for normal operation. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor (EOV for Ethernet (EOV for Ethernet) ...
Page 64
... PPC440EPx Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
Page 65
... Logic Supply Voltage I/O Supply Voltage Ethernet I/O Supply Voltage DDR2 (DDR1) SDRAM I/O Supply Voltage System Analog Supply Voltages Ethernet Analog Voltage USB Analog Voltages DDR2 (DDR1) SDRAM Reference Voltage AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Symbol EOV DD SOV ...
Page 66
... The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440EPx. See “Absolute Maximum Ratings” on page 65. 4. Startup sequencing of the power supply voltages is not required. A power-down cycle must complete (OV DD and V DD are below +0 ...
Page 67
... EBC and NAND flash interfaces. 1/GMCRXClk - GMII and MII mode 1/SMIIRefClk - SMII mode 1/GMC0RxClk and 1/GMC1RxClk - RGMII mode 1/USB2Clk - UTMI 1/TrcClk - instruction trace interface 1/IIC0Clk and 1/IIC1Clk - IIC interfaces 1/SPIClkOut - SPI AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Symbol C IN1 C IN2 C IN3 C ...
Page 68
... The analog voltages (AVdd, EAVdd, and UnAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before the PPC440EPx. A Separate filter, as shown below, is recommended for each voltage. • The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +50 mV. • ...
Page 69
... Typical current is estimated at 667MHz with V and T = +100°C with a typical process Maximum current is measured at 667MHz with V (DDR2), and T = +100°C, and best-case process (which drives worst-case power). C AMCC Proprietary 440EPx – PPC440EPx Embedded Processor +1.425V +1.5V 1.49 1.69 1.64 1.88 1.94 2.20 specified in the table and T = 100° ...
Page 70
... PPC440EPx Embedded Processor Table 17. Package Thermal Specifications Thermal resistance values for the TE-PBGA package in a convection environment at 6.3W are as follows: Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: 1 ...
Page 71
... V should be specified in Volts. I BE2 BE1 same. The small values require precision measurement and current sources. The calculated on chip (ball to ball) series resistance for the PPC440EPx thermal monitor circuit is 2.0 ohms. The thermal sensor reflects the PPC440EPx junction temperature. PPC440EPx C E TherMonA ...
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... PPC440EPx Embedded Processor Table 18. Clocking Specifications (continued) Symbol Parameter Processor (CPU) Clock F Frequency C T Period C MemClkOut and PLB Clock F Frequency C T Period C T High time CH MAL Clock F Frequency C T Period C Note: 1. SysClk supports spread spectrum clocking with a -1% down-spread and a 40 kHz or less modulation frequency. For a 33.33MHz minimum SysClk, the modulation frequency range of 33.00 MHz to 33.33 MHz is supported. 2. The maximum input cycle-to-cycle jitter is ± ...
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... The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected the system designer to ensure that any SSCG used with the PPC440EPx meets the above Important: requirements and does not adversely affect other aspects of the system. AMCC Proprietary 440EPx – ...
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... PPC440EPx Embedded Processor I/O Specifications Table 19. Peripheral Interface Clock Timings (Sheet Parameter PCIClk frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk high time PCIClk low time GMCMDClk frequency GMCMDClk period GMCMDClk high time GMCMDClk low time GMCTxClk frequency MII ...
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... UARTSerClk period UARTSerClk high time UARTSerClk low time USB2Clk frequency USB2Clk period USB2XtalIn/USB2XtalOut frequency USB2XtalIn/USB2XtalOut period USB2XtalIn/USB2XtalOut high time USB2XtalIn/USB2XtalOut low time AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Min Max 33.33MHz 83. 50% of nominal period 66% of nominal period 33% of nominal period ...
Page 76
... PPC440EPx Embedded Processor Table 19. Peripheral Interface Clock Timings (Sheet Parameter TmrClk frequency TmrClk period TmrClk high time TmrClk low time Notes the period the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock OPB frequency is 83 MHz ...
Page 77
... Figure 6. Input Setup and Hold Waveform Clock 1.25V(1.5V) Inputs Figure 7. Output Delay and Float Timing Waveform Clock 1.25V(1.5V) max min Outputs OH High (Drive) Float (High-Z) Low (Drive) AMCC Proprietary 440EPx – PPC440EPx Embedded Processor T min T min IS IH Valid max min OH Valid max T OV ...
Page 78
... PPC440EPx Embedded Processor Figure 8. Setup and Hold Timing Waveforms for RGMII Signals GMCnTxClk GMCnTxD/Ctl GMCnRxClk GMCnRxD/Ctl Table 20. RGMII I/O Timing Input (ns) Signal TskewR TskewR (min) (max) GMCnRxClk – GMCnRxD0:3 1.0 GMCnRxCtl 1.0 2.8 GMCnTxClk v GMCnTxD0:3 n/a GMCnTxCtl n/a Notes: 1 ...
Page 79
... GMCCrS GMCMDClk GMCMDIO GMCRxClk GMCRxD0:3 10 GMCTxD0:3 GMCRxDV 10 GMCRxEr 10 GMCTxClk GMCTxEr GMCTxEn Ethernet GMII Interface GMCCD GMCCrS GMCGTxClk GMCMDClk GMCMDIO GMCRxClk GMCRxD0:3 2 GMCTxD0:3 GMCRxDV 2 GMCRxEr 2 GMCTxEr GMCTxEn AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min ...
Page 80
... PPC440EPx Embedded Processor Table 21. I/O Specifications—PCI, USB, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. SMIISync is a weak driver. Redrive SMIISync when driving more than one load. ...
Page 81
... Hold Time (T min System Interface SysReset Halt SysErr GPIO00:11 GPIO12:25 GPIO26:48 GPIO49:63 Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min Output Current (mA) Clock I/O H I/O L (minimum) (minimum) n/a ...
Page 82
... PPC440EPx Embedded Processor Table 22. I/O Specifications—EBC, EBMI, DMA and NAND Flash Interfaces Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Signal Setup Time Hold Time (T min External Slave Peripheral Interface ...
Page 83
... The paths (traces) for the data and the associated data strobe signal should be routed with the same length between the PPC440EPx and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the capture logic at the same time the data is in transition. All of the following timing assumes a trace velocity of 167ps/in ...
Page 84
... PPC440EPx) between the DQS/DQ/DM and the clock (assuming nominal settings as specified in the PPC440EPx Users Manual). While the clock is now 500ps later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for T (± ...
Page 85
... The timing numbers in the following sections are obtained using a simulation that assumes a model as shown in Figure 9. The following diagram illustrates the relationship among the signals involved with a DDR write operation. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Output Current (mA) I/O H (maximum) 10 ...
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... PPC440EPx Embedded Processor Figure 10. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut Addr/Cmd DQS MemData T = Delay from falling edge of MemClkOut to rising/falling edge of signal (skew Setup time for address and command Hold time for address and command signals from MemClkOut ...
Page 87
... PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices. In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version of DQS. The amount of delay is user programmable. In the example shown in Figure 11, the delay is set to approximately 25% of the system clock ...
Page 88
... PPC440EPx Embedded Processor constant. Figure 11. DDR SDRAM DQS Read Timing MemClkOut DQS MemData Delayed DQS (data strobe) 88 Revision 1.30 – February 27, 2009 DQS delay Data Sheet AMCC Proprietary ...
Page 89
... Data Sheet Boot Configuration The PPC440EPx supports several configurable boot parameters that must be initialized prior to booting. These parameters are configured by one of several default boot options or programmed by data read from an IIC serial EEPROM (see “Serial EEPROM” below). Strap signals sampled during reset select which method is used to initialize the boot parameters (see “ ...
Page 90
... PPC440EPx Embedded Processor Revision Log Date Version 06/01/2005 06/03/2005 07/06/2005 08/29/2005 09/12/2005 10/03/2005 10/05/2005 11/14/2005 1.07 03/01/2006 1.08 03/15/2006 1.09 04/05/2006 1.10 04/24/2006 1.11 05/12/2006 1.12 05/15/2006 1.13 05/30/2006 1.14 07/12/2006 1.15 07/19/2006 1.16 11/02/2006 1.17 90 Contents of Modification Initial creation of document. ...
Page 91
... AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Contents of Modification Indicate that two USB analog voltages are needed with separate filters. Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals. Add information concerning address bus loading on DDR SDRAMs. ...
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... PPC440EPx Embedded Processor Date Version 02/27/2009 1.30 92 Contents of Modification Doc Issue 5025: Added C value to filter AVdd circuit on page 68. Doc Issue 5172: Replaced Figure 8 with new RGMII timing figure. Removed former Figure 9. Added new Table 20 with RGMII I/O Timing data. Removed RGMII timing data from former Table 20 (is now Table 21) ...
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... SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2009 Applied Micro Circuits Corporation. All Rights Reserved. AMCC Proprietary 440EPx – PPC440EPx Embedded Processor Applied Micro Circuits Corporation http://www.amcc.com 93 ...