MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 86
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC16M16A2P-75:DTR
Manufacturer Part Number
MT48LC16M16A2P-75:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC16M16A2P-75DTR.pdf
(87 pages)
Specifications of MT48LC16M16A2P-75:DTR
Lead Free Status / Rohs Status
Compliant
- Current page: 86 of 87
- Download datasheet (4Mb)
Figure 55: Clock Suspend During READ Burst
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
Note:
Internal
Address
clock
CKE
CLK
DQ
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
T0
READ
Bank,
Col n
T1
NOP
T2
NOP
D
OUT
86
T3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
OUT
T4
NOP
T5
NOP
256Mb: x4, x8, x16 SDRAM
D
OUT
T6
Don’t Care
NOP
D
© 1999 Micron Technology, Inc. All rights reserved.
OUT
Clock Suspend
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