HD3-6402R-9 Intersil, HD3-6402R-9 Datasheet - Page 5

• Manufacturer Part Number: HD3-6402R-9
• Description: 06F5779
• Manufacturer: Intersil

Specifications of HD3-6402R-9

• No. Of Channels: 8
• Uart Features: Programmable Word Length, Stop Bits And Parity, Automatic Data Formatting And Status Generation
• Supply Voltage Range: 4.5V To 5.5V
• Rohs Compliant: No

Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have
occurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is a
Interfacing with the HD-6402
SYSTEM
DIGITAL
RBR1-8, OE, PE
RRI INPUT
TBR1
TBR8
CONTROL
CONTROL
RB1
RB8
TRANSMITTER
CLOCK
RECEIVER
HD-6402
DRR
RRI
5
DR
FE
START BIT
TRO
RRI
FIGURE 2. RECEIVER TIMING (NOT TO SCALE)
A
FIGURE 5. TYPICAL SERIAL DATA LINK
RECEIVER
FIGURE 3. SERIAL DATA FORMAT
LSB
A
DRIVER
RS232
RS232
81/2 CLOCK CYCLES
71/2 CLOCK CYCLES
FIGURE 4.
START
5-8 DATA BITS
HD-6402
HD-6402
symmetrical square wave, the center of the start bit will be
located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searching
for the next start bit at the center of the first stop bit.
RECEIVER
DRIVER
RS232
RS232
B
BEGINNING OF FIRST STOP BIT
MSB
7 1/2 CLOCK CYCLES
C
1, 11/2 OR 2 STOP BITS
†
1 CLOCK CYCLE
COUNT 71/2 DEFINED
CENTER OF START BIT
RRI
TRO
TRANSMITTER
RECEIVER
HD-6402
CONTROL
CONTROL
PARITY
TBR1
TBR8
RB1
RB8
†
IF ENABLED
SYSTEM
DIGITAL