74LVT16245BDGG NXP Semiconductors, 74LVT16245BDGG Datasheet
74LVT16245BDGG
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74LVT16245BDGG Summary of contents
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V 16-bit transceiver; 3-state Rev. 07 — 29 March 2010 1. General description The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for V operation at 3 This device is a 16-bit transceiver featuring non-inverting ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range −40 °C to +85 °C 74LVT16245BDL 74LVTH16245BDL −40 °C to +85 °C 74LVT16245BDGG 74LVTH16245BDGG −40 °C to +85 °C 74LVT16245BEV −40 °C to +85 °C 74LVT16245BBQ 74LVTH16245BBQ 4. Functional diagram 1DIR 1A0 1A1 1A2 ...
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... NXP Semiconductors Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 2. IEC logic symbol 74LVT_LVTH16245B_7 Product data sheet 74LVT16245B; 74LVTH16245B 48 1OE G3 1 3EN1 [ BA ] 1DIR 3EN2 [ 2OE 24 6EN4 [ BA ] 2DIR 6EN5 [ 1A0 1A1 5 44 1A2 6 43 1A3 41 8 1A4 40 9 1A5 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVT16245B 74LVTH16245B 1 1DIR 2 1B0 1B1 3 GND 4 1B2 5 6 1B3 1B4 8 1B5 9 GND 10 11 1B6 12 1B7 2B0 13 2B1 14 GND 15 16 2B2 17 2B3 2B4 19 2B5 20 21 GND 22 2B6 2B7 23 2DIR 24 Fig 3. Pin configuration for SSOP48 and TSSOP48 ...
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... NXP Semiconductors terminal 1 index area (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SOT1134-1 (HXQFN60U) 74LVT_LVTH16245B_7 Product data sheet 74LVT16245B; 74LVTH16245B D1 A32 A31 A30 A29 D5 B20 B19 A1 A2 ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1, 24 1B0 to 1B7 11, 12 2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1OE, 2OE 48, 25 2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 1A0 to 1A7 ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C [1] T amb V input clamping voltage IK V HIGH-level output voltage LOW-level output voltage input leakage current I I power-off leakage current V ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter C off-state input/output io(off) capacitance [1] Typical values are measured at V [2] Unused pins GND. CC [3] This is the bus hold overdrive current required to force the input to the opposite logic state. ...
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... NXP Semiconductors 11. Waveforms Measurements points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay input (nAn, nBn) to output (nBn, nAn) nOE input nAn or nBn nBn or nAn Measurements points are given in V and V are typical voltage output levels that occur with the output load ...
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... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 9. Test data ...
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... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE ...
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... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 0.65 mm ball A1 index area ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.3 0.7 0. 0.2 0.6 0.35 OUTLINE VERSION IEC SOT702-1 Fig 11. Package outline SOT702-1 (VFBGA56) ...
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... NXP Semiconductors HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 0.5 mm terminal 1 index area A10 terminal 1 index area D1 Dimensions Unit max 0.50 0.05 0.35 4.1 mm nom 0.48 0.02 0.30 4.0 min 0.46 0.00 0.25 3.9 ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVT_LVTH16245B_7 20100329 • Modifications: 74LVT16245BBQ and 74LVTH16245BBQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVT_LVTH16245B_7 Product data sheet 74LVT16245B; 74LVTH16245B http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 07 — 29 March 2010 3.3 V 16-bit transceiver; 3-state © ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline ...