IDT5T907PAI IDT, Integrated Device Technology Inc, IDT5T907PAI Datasheet - Page 3

• Manufacturer Part Number: IDT5T907PAI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT5T907PAI

• Number Of Outputs: 10
• Operating Supply Voltage (max): 2.6V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 3.5ns
• Operating Supply Voltage (min): 2.4V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSSOP
• Quiescent Current: 30mA
• Input Frequency: 250MHz
• Duty Cycle: 60%
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION
NOTES:
1. Inputs are capable of translating the following interface standards. User can select between:
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
3. 3 level inputs are static inputs and must be tied to V
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
Symbol
IDT5T907
2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER
A/V
GND
V
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
pulses or be able to tolerate them in down stream circuitry.
RxS
TxS
V
G1
G2
GL
Qn
DDQ
A
DD
REF
I/O
O
I
I
I
I
I
I
I
Adjustable
Adjustable
Adjustable
3 Level
3 Level
LVTTL
LVTTL
LVTTL
Type
PWR
PWR
PWR
(5)
(5)
(5)
(3)
(3)
(1)
(1)
(2)
Description
Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input.
Complementary clock input. A/V
mode, A/V
voltage for A:
Gate for outputs Q
nously disabled to the level designated by GL
Gate for outputs Q
nously disabled to the level designated by GL
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Clock outputs
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in
conjunction with V
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, V
Power supply return for all power
REF
is connected to GND. For single-ended operation in differential mode, A/V
DD
2.5V LVTTL
1.8V LVTTL, eHSTL
HSTL
LVEPECL
or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
DDQ
1
6
through Q
through Q
to set the interface levels.
5
10
. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchro-
. When G2 is LOW, these outputs are enabled. When G2 is HIGH, these outputs are asynchro-
REF
is the "complementary" side of A if the input is in differential mode. If operating in single-ended
V
V
V
V
REF
REF
REF
REF
3
(4)
(4)
= 1250mV
= 900mV
= 750mV
= 1082mV
.
.
DDQ
should be connected to V
DDQ
INDUSTRIAL TEMPERATURE RANGE
voltage.
REF
should be set to the desired toggle
DD
.