IDT74ALVCH16903PV IDT, Integrated Device Technology Inc, IDT74ALVCH16903PV Datasheet

IDT74ALVCH16903PV

Manufacturer Part Number

IDT74ALVCH16903PV

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74ALVCH16903PV.pdf (13 pages)

Specifications of IDT74ALVCH16903PV

Logic Family

ALVC

Operating Supply Voltage (typ)

2.5/3.3V

Propagation Delay Time

6.4ns

Number Of Elements

Number Of Channels

Input Logic Level

LVTTL

Output Logic Level

LVTTL

Output Type

3-State

Package Type

SSOP

Polarity

Non-Inverting

Logical Function

Bus Transceiver/Register with Parity Checker

Operating Supply Voltage (min)

2.3V

Operating Supply Voltage (max)

3.6V

Quiescent Current (typ)

100nA

Technology

CMOS

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

Lead Free Status / Rohs Status

Not Compliant

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FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

CAPACITANCE

NOTE:

1. As applicable to the device type.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

2. V

3. This value is limited to 4.6V maximum.

IDT74ALVCH16903

3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

Symbol

OUT

machine model (C = 200pF, R = 0)

STG

TERM

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

OUT

terminals.

(2)

(3)

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

= 2.5V ± 0.2V

Terminal Voltage with Respect to GND

(Outputs Only)

Storage Temperature

DC Output Current

Continuous Clamp Current,

Continuous Clamp Current, V

Continuous Current through each

SK(o)

Input Capacitance

Output Capacitance

I/O Port Capacitance

< 0 or V

Parameter

or GND

(Output Skew) < 250ps

> V

Description

(1)

= +25°C, F = 1.0MHz)

Conditions

OUT

= 0V

< 0

= 0V

3.3V CMOS 12-BIT UNIVERSAL

BUS DRIVER WITH PARITY

CHECKER, DUAL 3-STATE

OUTPUTS AND BUS-HOLD

–0.5 to V

Typ.

–0.5 to +4.6

–65 to +150

–50 to +50

±100

Max

±50

–50

Max.

+0.5

(1)

Unit

° C

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

DESCRIPTION:

technology. This device has dual outputs and can operate as a buffer or an

edge-triggered register. In both modes, parity is checked on APAR, which

arrives one cycle after the data to which it applies. The YERR output, which is

produced one cycle after APAR, is open drain.

operates as an edge-triggered register. On the positive transition of the clock

(CLK) input and when the clock-enable (CLKEN) input is low, data setup at the

A inputs is stored in the internal registers. On the positive transition of CLK and

when CLKEN is high, only data setup at the 9A-12A inputs is stored in their

internal registers. When MODE is high, the device operates as a buffer and data

at the A inputs passes directly to the outputs. The 11A/YERREN serves a dual

purpose; it acts as a normal data bit and also enables YERR data to be clocked

into the YERR output register.

high; when parity input/output (PARI/O) is low, even parity is selected and when

PARI/O is high, odd parity is selected. When used in pairs and PAROE is low,

the parity sum is output on PARI/O for cascading to the second ALVCH16903.

When used in pairs and PAROE is high, PARI/O accepts a partial parity sum

from the first ALVCH16903.

YERR in either a normal logic state (high or low logic levels) or a high-impedance

state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the

capability to drive bus lines without need for interface or pullup components.

driver is capable of driving a moderate to heavy load while maintaining speed

performance.

whenever the input bus goes to a high-impedance. This prevents floating inputs

and eliminates the need for pull-up/down resistors.

This 12-bit universal bus driver is built using advanced dual metal CMOS

MODE selects one of the two data paths. When MODE is low, the device

When used as a single device, parity output enable (PAROE) must be tied

A buffered output-enable (OE) input can be used to place the 24 outputs and

The ALVCH16903 has been designed with a ±24mA output driver. This

The ALVCH16903 has “bus-hold” which retains the inputs’ last state

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903

JUNE 2006

DSC-4911/4

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IDT74ALVCH16903PV Summary of contents

Page 1

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, ...

Page 2

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER FUNCTIONAL BLOCK DIAGRAM MODE 56 CLK 1A-12A, APAR 13 (1A-8A Flip CLKEN Flop 5 (9A-12A, APAR) Flip Flop 28 PAROE FUNCTION TABLE (1) Inputs OE ...

Page 3

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER PIN CONFIGURATION GND ...

Page 4

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input ...

Page 5

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER OUTPUT DRIVE CHARACTERISTICS, xYx PORTS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL I High-Level Output Current OH I Low-Level Output Current OL NOTE ...

Page 6

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER OPERATING CHARACTERISTICS FOR BUFFER MODE, T Symbol Parameter C Power Dissipation Capacitance Outputs enabled PD C Power Dissipation Capacitance Outputs disabled PD OPERATING CHARACTERISTICS FOR REGISTER MODE, T Symbol Parameter ...

Page 7

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER SWITCHING CHARACTERISTICS Symbol Parameter f MAX t Propagation Delay, Buffer Mode PLH t xAx to xYx PHL t Propagation Delay, Both Modes PLH CLK to YERR t PHL t Propagation ...

Page 8

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 ...

Page 9

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER PARAMETER MEASUREMENT INFORMATION From Output Under Test 500Ω (see Note 1) Load Circuit TIMING 1.5V INPUT t su DATA 1.5V INPUT Voltage Waveforms Setup and ...

Page 10

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER LOAD CIRCUIT AND VOLTAGE WAVEFORMS From Output Under Test PARI/O NOTE includes probe and jig capacitance 2.7V AND 3.3V ± 0.3V CC 1.5V INPUT t ...

Page 11

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER PARAMETER MEASUREMENT INFORMATION From Output Under Test 500Ω (see Note 1) Load Circuit TIMING V INPUT t su DATA V CC/2 INPUT Voltage Waveforms Setup ...

Page 12

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER PARAMETER MEASUREMENT INFORMATION NOTES includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz ...

Page 13

IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER ORDERING INFORMATION IDT XX ALVC X Bus-Hold Family Temp. Range CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XXX XXX XX Device Type Package PA PAG 903 ...

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