E28F320J3A110 Intel, E28F320J3A110 Datasheet - Page 26

• Manufacturer Part Number: E28F320J3A110
• Manufacturer: Intel

Specifications of E28F320J3A110

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

256-Mbit J3 (x8/x16)
7.2
26
NOTES:
CE
or CE2 that disables the device (see
W12
W13
W15
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
2. A write operation can be initiated and terminated with either CE
3. Sampled, not 100% tested.
4. Write pulse width (t
5. Refer to
6. Write pulse width high (t
7. For array access, t
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V
W11
W1
W2
W3
W4
W5
W6
W7
W8
W9
#
X
during read-only operations. Refer to AC Characteristics–Read-Only Operations.
high (whichever goes high first). Hence, t
going low (whichever goes low first). Hence, t
(SR[1,3,4:5] = 0).
Table 9.
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
PEN
t
t
t
t
t
t
t
t
t
t
t
t
t
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
VPWH
WHGL
WHRL
QVVL
should be held at V
Table 14
Symbol
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
AVEH
EHRL
DVEH
EHAX
VPEH
EHGL
EHWH
EHDX
Write Operations
Write Operations
)
)
)
)
)
)
for valid A
)
)
)
)
AVQV
WP
) is defined from CE
WPH
is required in addition to t
RP# High Recovery to WE# (CE
CE
Write Pulse Width
Data Setup to WE# (CE
Address Setup to WE# (CE
CE
Data Hold from WE# (CE
Address Hold from WE# (CE
Write Pulse Width High
V
Write Recovery before Read
WE# (CE
V
PENH
PEN
PEN
IN
X
X
) is defined from CE
Table
(WE#) Low to WE# (CE
(WE#) Hold from WE# (CE
and D
Setup to WE# (CE
Hold from Valid SRD, STS Going High
until determination of block erase, program, or lock-bit configuration success
Versions
13).
X
) High to STS Going Low
IN
for block erase, program, or lock-bit configuration.
WP
X
or WE# going low (whichever goes low last) to CE
= t
WPH
Parameter
WLWH
X
X
X
WHGL
) Going High
X
or WE# going high (whichever goes high first) to CE
= t
) Going High
) High
X
WHWL
= t
) Going High
X
X
) Going Low
) High
for any accesses after a write.
ELEH
X
X
) High
) Going Low
= t
= t
EHEL
X
WLEH
or WE#.
= t
= t
WHEL
X
ELWH
high is defined at the first edge of CE0, CE1,
= t
.
EHWL
.
Min
70
50
55
30
35
1
0
0
0
0
0
0
Valid for All
Speeds
X
Max
500
or WE# going
X
or WE#
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Datasheet
1,2,3,8,9
Notes
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,6
1,2,3
1,2,7
1,2,8
1,2,
1,2,
1,2,