M29F040B120K1T Micron Technology Inc, M29F040B120K1T Datasheet - Page 9

• Manufacturer Part Number: M29F040B120K1T
• Manufacturer: Micron Technology Inc

Specifications of M29F040B120K1T

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
Table 7. Status Register Bits
Note: Unspecified data bits should be ignored.
Program
Program During Erase
Suspend
Program Error
Chip Erase
Block Erase before
timeout
Block Erase
Erase Suspend
Erase Error
Operation
Faulty Block Address
Good Block Address
Non-Erasing Block
Non-Erasing Block
Non-Erasing Block
Erasing Block
Erasing Block
Erasing Block
Any Address
Any Address
Any Address
Any Address
Address
DQ7
DQ7
DQ7
DQ7
0
0
0
0
0
1
0
0
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so may
or may not set DQ5 at ‘1’. In both cases, a succes-
sive Bus Read operation will show the bit is still ’0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
No Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ6
Data read as normal
DQ5
0
0
1
0
0
0
0
0
0
1
1
DQ3
–
–
–
1
0
0
1
1
–
1
1
M29F040B
No Toggle
No Toggle
No Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ2
–
–
–
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