LH28F800SGN-L70 Sharp Electronics, LH28F800SGN-L70 Datasheet - Page 15

• Manufacturer Part Number: LH28F800SGN-L70
• Manufacturer: Sharp Electronics

Specifications of LH28F800SGN-L70

• Cell Type: NOR
• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

automatically outputs status register data when
read (see Fig. 7). The CPU can detect the
completion of the set lock-bit event by analyzing the
RY/BY# pin output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when V
V
bit contents are protected against alteration.
A successful set block lock-bit operation requires
that the permanent lock-bit be cleared and RP# =
V
set, SR.1 and SR.4 will be set to "1" and the
operation will fail. Set block lock-bit operations while
V
should not be attempted. A successful set
permanent lock-bit operation requires that RP# =
V
SR.4 will be set to "1" and the operation will fail.
Set permanent lock-bit operations with V
V
attempted.
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear
permanent lock-bit not set and RP# = V
lock-bits can be cleared using the Clear Block Lock-
Bits command. If the permanent lock-bit is set, clear
block lock-bits operation is unable. See Table 5
for a summary of hardware and software write
protection options.
PPH1/2/3
HH
IH
HH
HH
. If it is attempted with the permanent lock-bit
. If it is attempted with RP# = V
< RP# < V
produce spurious results and should not be
Block
. In the absence of this high voltage, lock-
Lock-Bits
HH
produce spurious results and
CC
= V
command.
CC1/2/3/4
IH
and V
, SR.1 and
IH
With
HH
< RP# <
, block
PP
the
=
- 15 -
Clear block lock-bits option is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written,
the device automatically outputs status register data
when read (see Fig. 8). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-
Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable
clear block lock-bits operation can only occur when
V
block lock-bits operation is attempted while V
V
absence of this high voltage, the block lock-bit
contents are protected against alteration. A
successful clear block lock-bits operation requires
that the permanent lock-bit is not set and RP# =
V
set or RP# = V
and the operation will fail. A clear block lock-bits
operation with V
results and should not be attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values. Once the permanent lock-bit is set, it
cannot be cleared.
CC
PPLK
HH
PP
. If it is attempted with the permanent lock-bit
or V
= V
, SR.3 and SR.5 will be set to "1". In the
CC1/2/3/4
CC
transition out of valid range or RP#
IH
IH
, SR.1 and SR.5 will be set to "1"
and V
< RP# < V
LH28F800SG-L (FOR SOP)
PP
= V
HH
PPH1/2/3
produce spurious
. In a clear
PP
≤