LH28F800SGN-L70 Sharp Electronics, LH28F800SGN-L70 Datasheet - Page 28

• Manufacturer Part Number: LH28F800SGN-L70
• Manufacturer: Sharp Electronics

Specifications of LH28F800SGN-L70

• Cell Type: NOR
• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

6.2.3 DC CHARACTERISTICS (contd.)
NOTES :
1. All currents are in RMS unless otherwise noted. Typical
2. I
3. Includes RY/BY#.
4. Block erases, word writes, and lock-bit configurations are
SYMBOL
V
V
V
V
V
V
V
V
V
V
V
IL
IH
OL
OH1
OH2
PPLK
PPH1
PPH2
PPH3
LKO
HH
values at nominal V
currents are valid for all product versions (packages and
speeds).
selected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of I
I
inhibited when V
range between V
V
and V
CCWS
CCES
PPH1
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
V
Normal Operations
V
Word Write, Block Erase
or Lock-Bit Operations
V
Word Write, Block Erase
or Lock-Bit Operations
V
Word Write, Block Erase
or Lock-Bit Operations
V
RP# Unlock Voltage
PPH3
and I
PP
PP
PP
PP
CC
(max.) and V
and I
Lockout Voltage during
Voltage during
Voltage during
Voltage during
Lockout Voltage
CCR
(min.), and above V
CCES
PARAMETER
or I
PP
PPLK
CCW
are specified with the device de-
≤ V
CC
PPH2
(max.) and V
, respectively.
voltage and T
PPLK
(min.), between V
, and not guaranteed in the
PPH3
PPH1
(max.).
A
NOTE
= +25°C. These
3, 7
3, 7
3, 7
4, 7
(min.), between
7
7
8
PPH2
V
CCWS
CC
MIN.
–0.5
–0.4
0.85
11.4
11.4
V
V
2.0
2.4
2.7
4.5
2.0
(max.)
CC
CC
= 2.7 to 3.6 V
or
- 28 -
MAX.
+0.5
12.6
12.6
V
0.8
0.4
1.5
3.6
5.5
CC
5. Automatic Power Saving (APS) reduces typical I
6. CMOS inputs are either V
7. Sampled, not 100% tested.
8. Permanent lock-bit set operations are inhibited when
1 mA at 5 V V
operation.
inputs are either V
RP# = V
inhibited when the permanent lock-bit is set or RP# =
V
corresponding block lock-bit is set and RP# = V
permanent lock-bits is set. Block erase, word write, and
lock-bit configuration operations are not guaranteed with
V
V
IH
IH
MIN.
–0.5
–0.4
0.85
11.4
11.4
V
V
CC
2.0
2.4
4.5
2.0
—
. Block erases and word writes are inhibited when the
CC
CC
< RP# < V
= 5.0±0.5 V
IH
. Block lock-bit configuration operations are
MAX.
+0.5
0.45
12.6
12.6
V
0.8
1.5
5.5
—
CC
CC
HH
and 3 mA at 2.7 to 3.6 V V
and should not be attempted.
IL
LH28F800SG-L (FOR SOP)
UNIT
or V
V
V
V
V
V
V
V
V
V
V
V
V
IH
CC
.
V
I
I
V
I
I
V
I
V
I
Set permanent lock-bit
Override block lock-bit
OL
OH
OL
OH
OH
OH
CC
CC
CC
CC
±0.2 V or GND±0.2 V. TTL
= 2.0 mA (V
= –2.0 mA (V
= 5.8 mA (V
= –2.5 mA (V
= –2.5 µA
= –100 µA
= V
= V
= V
= V
CONDITIONS
CC
CC
CC
CC
TEST
Min.
Min.
Min.
Min.
CC
CC
= 3.3 V, 2.7 V)
= 3.3 V, 2.7 V)
CC
CC
CC
IH
= 5 V),
= 5 V),
in static
CCR
or the
to