LH28F016SUT-10 Sharp Electronics, LH28F016SUT-10 Datasheet - Page 4

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LH28F016SUT-10

Manufacturer Part Number
LH28F016SUT-10
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F016SUT-10

Cell Type
NOR
Density
16Mb
Access Time (max)
100ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
21/20Bit
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Program/erase Volt (typ)
4.5 to 5.5V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
8/16Bit
Number Of Words
2M/1M
Supply Current
60mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant

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Quantity
Price
Part Number:
LH28F016SUT-10
Manufacturer:
INTEL
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Part Number:
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Manufacturer:
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Quantity:
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LH28F016SU
PIN DESCRIPTION
4
DQ
CE
DQ
SYMBOL
A
A
RY
16
1
8
»
0
0
WE
RP
OE
, CE
A
- A
- DQ
- A
- DQ
»
/ BY
0
»
»
15
20
»
1
»
15
7
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
TYPE
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A
input buffer is turned off when BYTE is high).
WORD-SELECT ADDRESSES: Select a word within one 64K block. A
1 of 1024 rows, and A
latched during Data Writes.
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS : Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUTS : Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE
specifications are the same for both signals. Device Selection
falling edge of CE
RESET/POWER-DOWN: With RP
aborted and device is put into the deep power down mode. When the power is
turned on, RP
figuration. When the 3/5
at the power on/off, RP
When returning from Deep Power-Down, a recovery time of 400 ns
(V
low, any current or pending WSM operation(s) are terminated, and the device is
reset. All Status registers return to ready (with all status flags cleared). After
returning, the device is in read array mode.
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
NOTE:
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE
Pin Disable command is issued.
CC
+5.0 V ±0.5 V) is required to allow these circuits to power-up. When RP
CE
»
X
overrides OE
»
pin is turned to low in order to return the device to default con-
»
0
or CE
1
»
- A
»
is required to stay low in order to protect data from noise.
»
, and OE
pin is switched, or when the power transition is occurred, or
»
1
. The first rising edge of CE
5
selects 16 of 512 columns. These addresses are
»
0
, CE
NAME AND FUNCTION
»
0
»
»
overrides WE.
low, the device is reset, any current operation is
or CE
»
1
»
is high.
must be low to select the device. All timing
»
or CE
»
1
high, the device is de-selected and power
16M (1M × 16, 2M × 8) Flash Memory
»
0
, CE
»
1
are high), except if a RY
»
0
or CE
»
1
occ
disables the device.
urs with the latter
6
-
A
15
selects
»
goes
»
/ BY
0
»

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