LH28F640BFHE-PBTLHGA Sharp Electronics, LH28F640BFHE-PBTLHGA Datasheet - Page 6

• Manufacturer Part Number: LH28F640BFHE-PBTLHGA
• Manufacturer: Sharp Electronics

Specifications of LH28F640BFHE-PBTLHGA

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DQ
RY/BY#
Symbol
A
RST#
GND
WE#
WP#
CE#
OE#
V
0
0
NC
-A
-DQ
CC
21
15
OPEN DRAIN
OUTPUT
OUTPUT
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses. 64M: A
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code and partition configuration register code reads. Data pins float to high-
impedance (High Z) when the chip or outputs are deselected. Data is internally latched
during an erase or program cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (V
standby levels.
RESET: When low (V
which provides data protection. RST#-high (V
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WRITE PROTECT: When WP# is V
or program operation can be executed to the blocks which are not locked and not locked-
down. When WP# is V
READY/BUSY#: Indicates the status of the internal WSM (Write State Machine). When
low, WSM is performing an internal operation (block erase, full chip erase, (page buffer)
program or OTP program). RY/BY#-High Z indicates that the WSM is ready for new
commands, block erase is suspended and (page buffer) program is inactive, (page buffer)
program is suspended, or the device is in reset mode.
DEVICE POWER SUPPLY (2.7V-3.6V): With V
flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
GROUND: Do not float any ground pins.
Table 1. Pin Descriptions
LHF64FHG
IL
IH
), RST# resets internal automation and inhibits write operations
, lock-down is disabled.
IH
) deselects the device and reduces power consumption to
Name and Function
IL
, locked-down blocks cannot be unlocked. Erase
IH
0
CC
-A
) enables normal operation. After
≤V
21
LKO
, all write attempts to the
CC
voltage (see DC
Rev. 2.45
4