TB28F400BVT80 Intel, TB28F400BVT80 Datasheet - Page 20

• Manufacturer Part Number: TB28F400BVT80
• Manufacturer: Intel

Specifications of TB28F400BVT80

• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

4-MBIT SmartVoltage BOOT BLOCK FAMILY
3.3.2
The device status register indicates when a
program or erase operation is complete, and the
success or failure of that operation. To read the
status register write the Read Status (70H)
command to the CUI. This causes all subsequent
read operations to output data from the status
register until another command is written to the
CUI. To return to reading from the array, issue a
Read Array (FFH) command.
The status register bits are output on DQ
both byte-wide (x8) or word-wide (x16) mode. In the
word-wide mode the upper byte, DQ
outputs 00H during a Read Status command. In the
byte-wide mode, DQ
DQ
20
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE-SUSPEND STATUS (ESS)
SR.5 = ERASE STATUS (ES)
SR.4 = PROGRAM STATUS (DWS)
SR.3 = V
SR.2-SR.0 = RESERVED FOR FUTURE
WSMS
15
/A
7
–1
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase In Progress/Completed
1 = Error In Block Erasure
0 = Successful Block Erase
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
1 = V
0 = V
ENHANCEMENTS (R)
retains the low order address function.
STATUS REGISTER
PP
STATUS (VPPS)
PP
PP
OK
Low Detect, Operation Abort
ESS
6
8
–DQ
14
are tri-stated and
ES
(WSMS)
5
Table 8. Status Register Bit Definition
SEE NEW DESIGN RECOMMENDATIONS
0
–DQ
8
–DQ
DWS
4
7
, in
15
,
Check WSM bit first to determine Word/Byte
program or Block Erase completion, before
checking program or erase status bits.
When erase suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
When this bit is set to “1,” WSM has applied the
max number of erase pulses to the block and is
still unable to verify successful block erasure.
When this bit is set to “1,” WSM has attempted
but failed to program a byte or word.
The V
indication of V
level only after the Byte Write or Erase command
sequences have been entered, and informs the
system if V
status bit is not guaranteed to report accurate
feedback between V
These bits are reserved for future use and should
be masked out when polling the status register.
Important: The contents of the status register
are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if
status register contents change while being read.
CE# or OE# must be toggled with each subsequent
status read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, the SR.7 register will
indicate the status of the WSM, and will also hold
the bits indicating whether or not the WSM was
successful in performing the desired operation.
VPPS
3
PP
status bit does not provide continuous
PP
has not been switched on. The V
PP
level. The WSM interrogates V
R
2
PPLK
NOTES:
and V
R
PPH
1
.
R
0
PP
PP