TB28F400BVT80 Intel, TB28F400BVT80 Datasheet - Page 44
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TB28F400BVT80
Manufacturer Part Number
TB28F400BVT80
Description
Manufacturer
Intel
Datasheet
1.TB28F400BVT80.pdf
(57 pages)
Specifications of TB28F400BVT80
Density
4Mb
Access Time (max)
80ns
Interface Type
Parallel
Boot Type
Top
Address Bus
19/18Bit
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
-40C to 85C
Package Type
SOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
3/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
8/16Bit
Number Of Words
512K/256K
Supply Current
70mA
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TB28F400BVT80
Manufacturer:
INTEL
Quantity:
5 000
Part Number:
TB28F400BVT80
Manufacturer:
INTEL
Quantity:
20 000
4-MBIT SmartVoltage BOOT BLOCK FAMILY
4.9.1
When applying V
may be required before initiating device operation,
depending on the V
slower than 1V/100 µs (0.01 V/µs) then no delay is
NOTES:
1.
2.
3.
4.10
(T
NOTE:
1. Sampled, not 100% tested.
44
> 1V/100 s
C
C
V
Symbol
A
IN
OUT
1V/100 s
CC
= 25 °C, f = 1 MHz)
These requirements must be strictly followed to guarantee all other read and write specifications.
To switch between 3.3 V and 5 V operation, the system should first transition V
and then to the new voltage. Any time the V
pending or in progress.
These guidelines must be followed for any V
Ramp Rate
Capacitance
APPLYING V CC VOLTAGES
Input Capacitance
Output Capacitance
Parameter
CC
No delay required.
A delay time of 2 s is required before any device operation is initiated, including read
operations, command writes, program operations, and erase operations. This delay is
measured beginning from the time V
operation, 3.0 V for 3.3
voltage to the device, a delay
CC
ramp rate. If V
Note
1
1
SEE NEW DESIGN RECOMMENDATIONS
CC
CC
CC
supply drops below V
transition from GND.
ramps
0.3 V operation; and 4.5 V for 5 V operation).
Typ
10
6
Required Timing
CC
required. If V
V/µs), then a delay of 2 µs is required before
initiating
recommended during power-up to protect against
spurious write signals when V
and V
reaches V
CCMIN
CCMIN
, the chip may be reset, aborting any operations
device
Max
.
12
8
CCMIN
CC
CC
from the existing voltage range to GND,
ramps faster than 1V/100 µs (0.01
(2.7 V for 2.7 V–3.6 V
operation.
Unit
pF
pF
CC
RP#
V
V
IN
OUT
is between V
Conditions
= 0 V
= 0 V
=
GND
LKO
is