CY7C67200-48BAI Cypress Semiconductor Corp, CY7C67200-48BAI Datasheet - Page 14

• Manufacturer Part Number: CY7C67200-48BAI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C67200-48BAI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-08014 Rev. *G
Halt Enable (Bit 0)
Setting this bit to ‘1’ immediately initiates HALT mode. While
in HALT mode, only the CPU is stopped. The internal clock still
runs and all peripherals still operate, including the USB
engines. The power savings using HALT in most cases will be
minimal, but in applications that are very CPU intensive the
incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is
triggered. Upon exiting the HALT state, one or two instructions
Interrupt Enable Register [0xC00E] [R/W]
Register Description
The Interrupt Enable Register allows control of the hardware
interrupt vectors.
OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG
ID/OTG4.4V Valid hardware interrupt.
1: Enable OTG interrupt
0: Disable OTG interrupt
SPI Interrupt Enable (Bit 11)
The SPI Interrupt Enable bit enables or disables the following
three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA
Block Done.
1: Enable SPI interrupt
0: Disable SPI interrupt
Host/Device 2 Interrupt Enable (Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all
of the following Host/Device 2 hardware interrupts: Host 2
USB
WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP
or WakeUp from USB, Device 2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt
0: Disable Host 2 and Device 2 interrupt
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Done,
Interrupt
Host
Enable
HSS
R/W
15
0
7
0
-
2
USB
In Mailbox
Reserved
Interrupt
Enable
R/W
14
0
6
0
-
SOF/EOP,
Out Mailbox
Figure 12. Interrupt Enable Register
Interrupt
Enable
R/W
13
0
5
0
-
Host
Reserved
Interrupt
2
Enable
OTG
R/W
12
0
4
1
-
immediately following the HALT instruction may be executed
before the waking interrupt is serviced (you may want to follow
the HALT instruction with two NOPs).
1: Enable Halt Mode
0: No Function
Reserved
All reserved bits must be written as ‘0’.
Host/Device 1 Interrupt Enable (Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all
of the following Host/Device 1 hardware interrupts: Host 1
USB
WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP
or WakeUp from USB, Device 1 Endpoint n.
1: Enable Host 1 and Device 1 interrupt
0: Disable Host 1 and Device 1 interrupt
HSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following
High-speed Serial Interface hardware interrupts: HSS Block
Done, and HSS RX Full.
1: Enable HSS interrupt
0: Disable HSS interrupt
In Mailbox Interrupt Enable (Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the
HPI: Incoming Mailbox hardware interrupt.
1: Enable MBXI interrupt
0: Disable MBXI interrupt
Out Mailbox Interrupt Enable (Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the
HPI: Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt
0: Disable MBXO interrupt
Interrupt
Done,
Interrupt
Enable
Enable
UART
R/W
R/W
SPI
11
0
3
0
Host
Reserved
Interrupt
Enable
GPIO
R/W
10
0
-
2
0
1
USB
Host/Device 2
Interrupt
Interrupt
Enable
Timer 1
Enable
R/W
R/W
SOF/EOP,
9
0
1
0
CY7C67200
Page 14 of 78
Host/Device 1
Interrupt
Interrupt
Enable
Timer 0
Enable
R/W
Host
R/W
8
0
0
0
1
[+] Feedback