CY7C67200-48BAI Cypress Semiconductor Corp, CY7C67200-48BAI Datasheet - Page 20

• Manufacturer Part Number: CY7C67200-48BAI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C67200-48BAI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-08014 Rev. *G
Host n Control Register [R/W]
Register Description
The Host n Control register allows high-level USB transaction
control.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission
of a preamble packet before all low-speed packets. This bit
should only be set when communicating with a low-speed
device.
1: Enable Preamble packet
0: Disable Preamble packet
Sequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next
packet. This bit has no effect on receiving data packets;
sequence checking must be handled in firmware.
1: Send DATA1
0: Send DATA0
Sync Enable (Bit 5)
The Sync Enable bit synchronizes the transfer with the SOF
packet in full-speed mode and the EOP packet in low-speed
mode.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Control Register 0xC080
• Host 2 Control Register 0xC0A0
Preamble
Enable
R/W
15
0
7
0
-
Sequence
Select
R/W
14
0
6
0
-
Figure 18. Host n Control Register
Enable
Sync
R/W
13
0
5
0
-
Enable
R/W
ISO
12
4
0
0
-
1: The next enabled packet will be transferred after the SOF
or EOP packet is transmitted
0: The next enabled packet will be transferred as soon as the
SIE is free
ISO Enable (Bit 4)
The ISO Enable bit enables or disables an Isochronous trans-
action.
1: Enable Isochronous transaction
0: Disable Isochronous transaction
Arm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction.
This bit is automatically cleared to ‘0’ when a transaction is
complete.
1: Arm endpoint and begin transaction
0: Endpoint disarmed
Reserved
All reserved bits must be written as ‘0’.
Reserved
11
3
0
0
-
-
Reserved
10
2
0
0
-
-
1
0
9
0
-
-
CY7C67200
Page 20 of 78
Enable
R/W
Arm
0
0
8
0
-
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