SB21150AC Intel, SB21150AC Datasheet - Page 109

• Manufacturer Part Number: SB21150AC
• Manufacturer: Intel

Specifications of SB21150AC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

14.0
14.1
14.2
Preliminary
Datasheet
Reset
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
Primary Interface Reset
The 21150 has one reset input, p_rst_l.
When p_rst_l is asserted, the following events occur:
The p_rst_l asserting and deasserting edges can be asynchronous to p_clk and s_clk.
Secondary Interface Reset
The 21150 is responsible for driving the secondary bus reset signal, s_rst_l. The 21150 asserts
s_rst_l when any of the following conditions is met:
Signal s_rst_l remains asserted until a configuration write operation clears the secondary reset bit
and the secondary clock serial mask has been shifted in.
When s_rst_l is asserted, all secondary PCI interface control signals, including the secondary grant
outputs, are immediately tristated. Signals s_ad, s_cbe_l, and s_par are driven low for the duration
of s_rst_l assertion. All posted write and delayed transaction data buffers are reset; therefore, any
transactions residing in 21150 buffers at the time of secondary reset are discarded.
When s_rst_l is asserted by means of the secondary reset bit, the 21150 remains accessible during
secondary interface reset and continues to respond to accesses to its configuration space from the
primary interface.
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The 21150 immediately tristates all primary and secondary PCI interface signals.
The 21150 performs a chip reset.
Registers that have default values are reset.
Appendix A lists the values of all configuration space registers after reset.
Signal p_rst_l is asserted.
Signal s_rst_l remains asserted as long as p_rst_l is asserted and does not deassert until p_rst_l
is deasserted and the secondary clock serial disable mask has been shifted in (23 or 46 clock
cycles after p_rst_l deassertion).
The secondary reset bit in the bridge control register is set.
Signal s_rst_l remains asserted until a configuration write operation clears the secondary reset
bit and the secondary clock serial mask has been shifted in.
The chip reset bit in the diagnostic control register is set.
21150
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