SB21150AC Intel, SB21150AC Datasheet - Page 66

• Manufacturer Part Number: SB21150AC
• Manufacturer: Intel

Specifications of SB21150AC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

21150
5.3
58
Figure 16. I/O Transaction Forwarding in ISA Mode
Caution:
Memory Address Decoding
The 21150 has three mechanisms for defining memory address ranges for forwarding of memory
transactions:
This section describes the first two mechanisms.
To enable downstream forwarding of memory transactions, the memory enable bit must be set in
the command register in 21150 configuration space. To enable upstream forwarding of memory
transactions, the master enable bit must be set in the command register. Setting the master enable
bit also allows upstream forwarding of I/O transactions.
If any 21150 configuration state affecting memory transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that memory transactions are
ongoing on the secondary bus, 21150 response to the secondary bus memory transactions is not
predictable. Configure the memory-mapped I/O base and limit address registers, prefetchable
memory base and limit address registers, and VGA mode bit before setting the memory enable and
•
•
•
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
Primary
Interface
Note:
In this example:
I/O Base Address = 0000 4000h
I/O Limit Address = 0000 4FFFh
ISA Enable = 1
5000h - FFFFh
4D00h - 4FFFh
4C00h - 4CFFh
4900h - 4BFFh
4800h - 48FFh
4500h - 47FFh
4400h - 44FFh
4100h - 43FFh
4000h - 40FFh
0000h - 3FFFh
I/O Address Space
Section 5.4.1
describes VGA mode.
Secondary
Interface
LJ-04637.AI5
Preliminary
Datasheet