SB21150AC Intel, SB21150AC Datasheet - Page 70

• Manufacturer Part Number: SB21150AC
• Manufacturer: Intel

Specifications of SB21150AC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

21150
5.4
5.4.1
62
within the memory-mapped I/O or VGA memory range). A dual address memory transaction is
forwarded downstream from the primary interface if it falls within the address range defined by the
prefetchable memory base address, prefetchable memory base address upper 32 bits, prefetchable
memory limit address, and prefetchable memory limit address upper 32 bits registers. If the dual
address transaction initiated on the secondary interface falls outside this address range, it is
forwarded upstream to the primary interface. The 21150 does not respond to a dual address
transaction initiated on the primary interface that falls outside this address range, or to a dual
address transaction initiated on the secondary interface that falls within the address range.
If the secondary interface prefetchable memory space straddles the first 4GB address boundary, the
prefetchable memory base address upper 32 bits register is set to 0, while the prefetchable memory
limit address upper 32 bits register is initialized to a nonzero value. Single address cycle memory
transactions are compared to the prefetchable memory base address register only. A transaction
initiated on the primary interface is forwarded downstream if the address is greater than or equal to
the base address. A transaction initiated on the secondary interface is forwarded upstream if the
address is less than the base address. Dual address transactions are compared to the prefetchable
memory limit address and the prefetchable memory limit address upper 32 bits registers. If the
address of the dual address transaction is less than or equal to the limit, the transaction is forwarded
downstream from the primary interface and is ignored on the secondary interface. If the address of
the dual address transaction is greater than this limit, the transaction is ignored on the primary
interface and is forwarded upstream from the secondary interface.
The prefetchable memory base address upper 32 bits register is located at configuration Dword
offset 28h, and the prefetchable memory limit address upper 32 bits register is located at
configuration Dword offset 2Ch. Both registers are reset to 0. See
how transactions are forwarded using both the memory-mapped I/O range and the prefetchable
memory range.
VGA Support
The 21150 provides two modes for VGA support:
VGA Mode
When a VGA-compatible device exists downstream from the 21150, set the VGA mode bit in the
bridge control register in configuration space to enable VGA mode. When the 21150 is operating in
VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory
and VGA I/O registers, regardless of the values of the 21150 base and limit address registers. The
21150 ignores transactions initiated on the secondary interface addressing these locations.
The VGA frame buffer consists of the following memory address range:
Read transactions to frame buffer memory are treated as nonprefetchable. The 21150 requests only
a single data transfer from the target, and read byte enable bits are forwarded to the target bus.
•
•
VGA mode, supporting VGA-compatible addressing
VGA snoop mode, supporting VGA palette forwarding
000A 0000h—000B FFFFh
Figure 17
Preliminary
for an illustration of
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