71V424L10PH IDT, Integrated Device Technology Inc, 71V424L10PH Datasheet

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71V424L10PH

Manufacturer Part Number
71V424L10PH
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.71V424L10PH.pdf (9 pages)

Specifications of 71V424L10PH

Density
4Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
19b
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
165mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Word Size
8b
Number Of Words
512K
Lead Free Status / Rohs Status
Not Compliant
Features
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
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Functional Block Diagram
©2008 Integrated Device Technology, Inc.
Bidirectional data inputs and outputs directly
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
I/O
0
- I/O
A
A
18
7
0
WE
OE
CS
•
•
•
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
8
ADDRESS
DECODER
8
CONTROL
LOGIC
1
Description
as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
pin, 400 mil TSOP.
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
The IDT71V424 has an output enable pin which operates as fast as
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
•
•
•
MEMORY ARRAY
I/O CONTROL
4,194,304-BIT
IDT71V424S/YS/VS
IDT71V424L/YL/VL
SEPTEMBER 2008
3622 drw 01
8
DSC-3622/07

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71V424L10PH Summary of contents

Page 1

Features ◆ ◆ ◆ ◆ ◆ 512K x 8 advanced high-speed CMOS Static RAM ◆ ◆ ◆ ◆ ◆ JEDEC Center Power / GND pinout for reduced noise ◆ ◆ ◆ ◆ ◆ Equal access and cycle times — Commercial ...

Page 2

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Pin Configuration I I SO36 I/O 2 ...

Page 3

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Absolute Maximum Ratings Symbol Rating V Supply Voltage Relative Terminal Voltage Relative IN OUT Temperature Under Bias BIAS ...

Page 4

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load AC Test Loads +1.5V I 50Ω 0 Figure ...

Page 5

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) AC Electrical Characteristics (V = 3.3V ± 10%, Commercial and Industrial Temperature Ranges) CC Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip ...

Page 6

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Timing Waveform of Read Cycle No. 1 ADDRESS OE CS DATA OUT SUPPLY CC CURRENT I SB Timing Waveform of Read Cycle No. 2 ADDRESS DATA ...

Page 7

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS DATA OUT DATA IN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ...

Page 8

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Ordering Information Commercial and Industrial Temperature Ranges 6.42 8 ...

Page 9

IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Datasheet Document History 8/13/99 Updated to new format Pg. 2 Removed SO44-1 from TSOP pinout Pg. 7 Revised footnotes on Write Cycle No. 1 diagram Removed footnote for t ...

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