PCF8578H NXP Semiconductors, PCF8578H Datasheet - Page 14

• Manufacturer Part Number: PCF8578H
• Manufacturer: NXP Semiconductors

Specifications of PCF8578H

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Pin Count: 64
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.5
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor R
For normal use a value of 330 k is recommended.
The clock signal, for cascaded PCF8579s, is output at
CLK and has a frequency
and 1 : 32) or
frequency.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. R
2003 Apr 14
LCD row/column driver for
dot matrix graphic displays
To avoid capacitive coupling, which could adversely affect oscillator
stability, R
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to R
Fig.9
OSCILLATOR
FREQUENCY
f OSC
(kHz)
f
OSC
OSC
Internal clock
10
10
12288
12288
10
3
2
1
(2)
= 330 k .
10
Oscillator frequency as a function of
external oscillator resistor, R
OSC
(Hz)
1
should be placed as closely as possible to the OSC
8
(multiplex rate 1 : 24) of the oscillator
10
OSC
2
FRAME FREQUENCY
.
1
6
(multiplex rate 1 : 8, 1 : 16
f
SYNC
64
64
10
3
(Hz)
R
OSC
OSC
OSC
.
MSA837
, see Fig.9.
(k )
10
4
MULTIPLEX RATE (n)
1 : 8, 1 : 16, 1 : 32
14
7.6
If an external clock is used, OSC must be connected to
V
summarizes the nominal CLK and SYNC frequencies.
7.7
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
7.8
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
open-circuit.
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
1 : 24
DD
and the external clock signal to CLK. Table 4
External clock
Timing generator
Row/column drivers
DIVISION
RATIO
6
8
CLOCK FREQUENCY
Product specification
f
CLK
PCF8578
2048
1536
(Hz)