83940DYLF IDT, Integrated Device Technology Inc, 83940DYLF Datasheet - Page 11

• Manufacturer Part Number: 83940DYLF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 83940DYLF

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

83940DY
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here
F
F
F
IGURE
IGURE
IGURE
CMR
2A. PCLK/nPCLK I
2C. PCLK/nPCLK I
2E. PCLK/nPCLK I
3.3V
3.3V
input requirements. Figures 2A to 2F show interface
2.5V
LVPECL
CML
BY AN
BY A
BY AN
SSTL
LOCK
3.3V LVPECL D
O
Zo = 50 Ohm
Zo = 50 Ohm
SSTL D
PEN
I
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 60 Ohm
Zo = 60 Ohm
NPUT
C
OLLECTOR
SWING
I
NTERFACE
RIVER
NPUT
NPUT
NPUT
3.3V
R1
50
2.5V
R3
120
3.3V
R3
125
and V
R1
120
R1
84
D
D
D
R2
50
RIVER
RIVEN
RIVEN
RIVEN
CML D
R4
120
R2
120
R4
125
OH
R2
84
PCLK
nPCLK
must meet the V
3.3V
PCLK
nPCLK
PCLK
nPCLK
3.3V
RIVER
HiPerClockS
PCLK/nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
Input
HiPerClockS
LVPECL-
www.idt.com
PP
11
are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver
termination requirements.
F
F
F
IGURE
IGURE
IGURE
3.3V
3.3V
TO
3.3V
2B. PCLK/nPCLK I
3.3V LVPECL
2D. PCLK/nPCLK I
2F.
LVDS
-LVCMOS / LVTTL F
CML Built-In Pullup
R5
100 - 200
BY A
PCLK/nPCLK I
BY A
BY A
Zo = 50 Ohm
Zo = 50 Ohm
B
R6
100 - 200
3.3V LVPECL D
3.3V LVDS D
UILT
Zo = 50 Ohm
Zo = 50 Ohm
-I
R5
100
N
Zo = 50 Ohm
Zo = 50 Ohm
P
ULLUP
NPUT
NPUT
NPUT
C1
C2
L
C1
C2
RIVER
OW
CML D
D
D
D
3.3V
R3
84
ICS83940D
RIVER WITH
R1
125
RIVEN
RIVEN
RIVEN
R1
100
3.3V
R3
1K
R1
1K
S
R4
84
ANOUT
R2
125
KEW
RIVER
R4
1K
PCLK
nPCLK
R2
1K
REV. B AUGUST 9, 2010
3.3V
PCLK
nPCLK
AC C
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
, 1-
3.3V
3.3V
B
HiPerClockS
PCL K/n PC LK
HiPerClockS
PCLK/nPCLK
TO
UFFER
OUPLE
-18