CA91L8260B-100CE IDT, Integrated Device Technology Inc, CA91L8260B-100CE Datasheet - Page 12

• Manufacturer Part Number: CA91L8260B-100CE
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of CA91L8260B-100CE

• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

QSpan
PowerQUICC
Interconnect Device
QSpan II provides the most cost-effective,
high performing PCI interface in the
smallest footprint on the market
(17 mm x 17 mm).
QSpan II is the industry-proven leader in bridging
Motorola's range of communications processors to
standard PCI buses in the latest communications
systems. QSpan II is a direct-connect PCI bridge for
the Motorola PowerQUICC™ (MPC8xx), and QUICC™
(MC68360), and processors.
The QSpan II contains an integrated PCI Bus Arbiter
which allows designers to save board real estate and
cost. As a result, QSpan II is the ideal choice as a
proven, low latency device that brings PCI-based
products to market faster and at less cost. The device
comes with a comprehensive Design Support Tools
(DST) suite that lets designers test it in their specific
working environment and design supporting software
quickly and easily.
™
II: Proven
™
-to-PCI System
Redefining board architecture
Benefits
• The QSpan II advanced features, including integrated PCI
• Industry-proven PCI System Interconnect device
• QSpan II Design Support Tools reduces customer's design hours
• Backwards compatible with QSpan
Arbiter, and the industry's first and smallest package- almost 50
per cent smaller than the original QSpan and our competitors -
enable designers to develop lower cost, sophisticated systems
with increasingly higher channel density
and time-to-market
QSpan II block diagram
Posted Writes, Prefetched Reads,
Posted Writes, Prefetched Reads,
Hot Swap
Controller
Delayed Single Reads/Writes
Delayed Single Reads/Writes
Up to 7
external
bus masters
Hot Swap
Friendly
PCI Bus
QBus Slave Channel
IDMA/DMA Channel
Arbiter
PCI Target Channel
Direct/Linked List Mode
Configuration Registers
Register Channel
Interrupt Channel
PCI/QBus Interrupts,
Mailbox Registers
FIFO-based,
Four FIFO
Messaging
IEEE1149.1
Boundary
Scan
JTAG
TM
I
2
O
8091862_BK001_02