M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet
M50LPW040K1
Specifications of M50LPW040K1
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M50LPW040K1 Summary of contents
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... Program other Blocks during Erase Suspend FOR USE in PC BIOS APPLICATIONS ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 26h August 2004 4 Mbit (512Kb x8, Uniform Block) 3V Supply Low Pin Count Flash Memory TSOP40 ( 20mm Figure 1. Logic Diagram (LPC Interface) ID0-ID2 GPI0- GPI4 ...
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M50LPW040 Figure 2. Logic Diagram (A/A Mux Interface A0-A10 RC M50LPW040 Figure 3. TSOP Connections A10 ...
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... PC BIOS on the Low Pin Count bus for these PC Chipsets. The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting Motherboard. The memory is offered in TSOP40 (10 x 20mm) and PLCC32 packages and it is supplied with all the bits erased (set to ’ ...
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M50LPW040 Table 2. Memory Identification Input Configuration Memory Number ID2 1 (Boot floating floating floating floating ...
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Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL, is set Low Program and Block Erase IL operations in the Top ...
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M50LPW040 Table 4. Absolute Maximum Ratings Symbol Ambient Operating Temperature (Temperature Range Option Ambient Operating Temperature (Temperature Range Option 5) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage ...
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Table 5. Block Addresses Size Block Address Range (Kbytes) Number 64 70000h-7FFFFh 64 60000h-6FFFFh 64 50000h-5FFFFh 64 40000h-4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 64 00000h-0FFFFh Note: For A19 value, refer to Table 2. Bus Read. Bus Read operations read ...
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... Data transfer is two CLK cycles, starting with the least XXXX O significant nibble. The LPC Flash Memory drives LAD0-LAD3 to 1111b to 1111b O indicate a turnaround cycle. 1111b The LPC Flash Memory floats its outputs, the host takes N/A (float) control of LAD0-LAD3. CYCTYPE ADDR TAR SYNC + DIR ...
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... The LPC Flash Memory drives LAD0-LAD3 to 0000b, 0000b O indicating it has received data or a command. The LPC Flash Memory drives LAD0-LAD3 to 1111b, 1111b O indicating a turnaround cycle. 1111b The LPC Flash Memory floats its outputs and the host takes N/A (float) control of LAD0-LAD3. CYCTYPE START ADDR DATA + DIR ...
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... Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, V Enable, W, must be Low, V Outputs are latched on the rising edge of Write use by Flash Enable, W. See Figure 13, A/A Mux Interface faster factory Write AC Waveforms, and Table 25, A/A Mux Interface Write AC Characteristics, for details of the timing requirements ...
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Read Memory Array Command. The Read Mem- ory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return ...
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M50LPW040 Table 11. Commands Command Read Memory Array Read Status Register Read Electronic Signature Program Quadruple Byte Program Chip Erase Block Erase Clear Status Register Program/Erase Suspend Program/Erase Resume Invalid/Reserved Note: X Don’t Care, PA Program Address, PD Program Data, ...
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Table 12. Program and Erase Times ( 70°C or –20 to 85° Parameter Byte Program Quadruple Byte Program Chip Erase Block Program Block Erase Program/Erase Suspend to Program pause Program/Erase Suspend to Block Erase pause ...
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M50LPW040 Table 13. Status Register Bits Operation Program active Program suspended Program completed successfully Program failure due to V Error PP Program failure due to Block Protection (LPC Interface only) Program failure due to cell failure Erase active Block Erase ...
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Controller has applied the maximum number of pulses to the block(s) and still failed to verify that the block(s) has erased correctly. Once the Erase Status bit is set to ‘1’ it can only be reset to ‘0’ by ...
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M50LPW040 Table 14. Low Pin Count Register Configuration Map Mnemonic T_BLOCK_LK Top Block Lock Register (Block 7) T_MINUS01_LK Top Block [-1] Lock Register (Block 6) T_MINUS02_LK Top Block [-2] Lock Register (Block 5) T_MINUS03_LK Top Block [-3] Lock Register (Block ...
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Table 15. Lock Register Bit Definitions Bit Bit Name Value 7-3 ‘1’ 2 Read-Lock ‘0’ ‘1’ 1 Lock-Down ‘0’ ‘1’ 0 Write-Lock ‘0’ Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to ...
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M50LPW040 Table 17. LPC Interface AC Measurement Conditions Parameter V Supply Voltage CC Load Capacitance ( Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 7. LPC Interface AC Testing Input Output ...
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Table 18. A/A Mux Interface AC Measurement Conditions Parameter V Supply Voltage CC Load Capacitance ( Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 8. A/A Mux Interface AC Testing Input ...
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M50LPW040 Table 20. DC Characteristics ( 70°C or –20 to 85° Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V (INIT) INIT Input High Voltage IH V (INIT) INIT Input Low ...
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Table 21. LPC Interface Clock Characteristics ( 70°C or –20 to 85° Symbol Parameter (1) t CLK Cycle Time CYC t CLK High Time HIGH t CLK Low Time LOW CLK Slew Rate Note: 1. ...
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M50LPW040 Table 22. LPC Interface AC Signal Timing Characteristics ( 70°C or –20 to 85° PCI Symbol Symbol t t CLK to Data Out CHQV val CLK to Active ( CHQX (Float ...
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Table 23. Reset AC Characteristics ( 70°C or –20 to 85° Symbol Parameter INIT Reset Pulse Width PLPH INIT Low to Reset PLRH RP or INIT Slew Rate t ...
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M50LPW040 Table 24. A/A Mux Interface Read AC Characteristics ( 70°C or –20 to 85° Symbol Parameter t Read Cycle Time AVAV t Row Address Valid to RC Low AVCL t RC Low to Row ...
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Table 25. A/A Mux Interface Write AC Characteristics ( 70°C or –20 to 85° Symbol Parameter t Write Enable Low to Write Enable High WLWH t Data Valid to Write Enable High DVWH t Write ...
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M50LPW040 Figure 13. A/A Mux Interface Write AC Waveforms Write erase or program setup A0-A10 R1 tCLAX tAVCL RC tWHWL tWLWH DQ0-DQ7 26/36 Write erase confirm or Automated erase valid address and data or program ...
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Figure 14. Program Flowchart and Pseudo Code Start Write 40h or 10h Write Address & Data Read Status Register YES YES YES LPC Interface Only YES End Note: ...
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M50LPW040 Figure 15. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write Address ...
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Figure 16. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write a read Command Read data from another address Write D0h Program Continues NO ...
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M50LPW040 Figure 17. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 80h Write 10h Read Status Register YES YES b4 YES YES End Note: ...
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Figure 18. Block Erase Flowchart and Pseudo Code Start Write 20h Write Block Address & D0h Read Status Register YES YES b4 YES YES LPC Interface b1 = ...
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M50LPW040 Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Read data from another block or Program Write D0h Erase Continues 32/36 NO ...
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Table 26. Ordering Information Scheme Example: Device Type M50 Architecture LP = Low Pin Count Interface Operating Voltage W = 3.0 to 3.6V Device Function 040 = 4 Mbit (512Kb x8), Uniform Block Package N = TSOP40 ...
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M50LPW040 TSOP40 – 40 lead Plastic Thin Small Outline 20mm, Package Outline TSOP-a Note: Drawing is not to scale. TSOP40 – 40 lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol Typ ...
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PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol Typ ...
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M50LPW040 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...