M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 2

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Figure 2. Logic Diagram (A/A Mux Interface)
Figure 3. TSOP Connections
2/36
A0-A10
RC
RP
IC
W
G
11
M50LPW040
V CC
V SS
IC (V IH )
V CC
V PP
A10
V PP
NC
NC
NC
NC
NC
NC
RC
NC
NC
RP
A9
A8
A7
A6
A5
A4
IC (V IL )
GPI4
GPI3
GPI2
GPI1
GPI0
V CC
8
V PP
CLK
TBL
WP
NC
NC
NC
NC
NC
NC
NC
NC
RP
DQ0-DQ7
RB
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1
10
11
20
M50LPW040
DESCRIPTION
The M50LPW040 is a 4 Mbit (512Kb x8) non-
volatile memory that can be read, erased and
reprogrammed.
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
40
31
30
21
individually
V SS
V CC
LFRAME
INIT
RFU
RFU
RFU
RFU
RFU
V CC
V SS
V SS
LAD3
LAD2
LAD1
LAD0
ID0
ID1
ID2
RFU
These
V SS
V CC
W
G
RB
DQ7
DQ6
DQ5
DQ4
V CC
V SS
V SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
to
operations
prevent
accidental
can
AI05437
be