SC68C562C1A NXP Semiconductors, SC68C562C1A Datasheet - Page 6

• Manufacturer Part Number: SC68C562C1A
• Manufacturer: NXP Semiconductors

Specifications of SC68C562C1A

• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
2004 Mar 29
X2/IDCN
RESETN
RxDA, RxDB
TxDA, TxDB
RTxCA, RTxCB
TRxCA, TRxCB
CTSA/BN,
LCA/BN
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GPI2A/BN
CMOS Dual universal serial communications controller
(CDUSCC)
MNEMONIC
40, 14
39, 15
43, 11
44, 10
35, 19
42, 12
37, 17
36, 18
38, 16
48, 5
PIN
46
8
TYPE
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
operating in local loopback mode. If external transmitter clock is specified for the channel, the data is
mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be
control, it can be used as a general purpose input when not in full-duplex single address DMA mode.
connected between pins X1 and X2. This pin can be programmed to provide an interrupt daisy chain
active-LOW output which propagates the IACKN signal to lower priority devices, if no active interrupt
transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output
DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the
Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is
is pending. This pin should be left floating when an external clock is used on X1 and X2 is not used
as an interrupt daisy chain output. When a crystal is used, a capacitor must be connected from this
pin to ground.
Master Reset: Active-LOW. A LOW on this pin resets the transmitters and receivers and resets the
registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is
required.
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external
receiver clock is specified for the channel, the input is sampled on the rising edge of the clock.
Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is in the marking (HIGH) condition when the transmitter is disabled or when the channel is
shifted on the falling edge of the clock.
Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the
receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the transmitter shift clock (1X), or the receiver sampling clock (1X).
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter,
counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output,
the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X),
The receiver BRG clock (16X), or the internal system clock (X1
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-LOW. The signal can be pro-
grammed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic
level transitions on this input and can be programmed to generate an interrupt when a transition
occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is as-
serted and negated by CDUSCC commands. This output provides the means of controlling external
loop interface hardware to go on-line and off-line without disturbing operation of the loop.
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-LOW input, it acts as an enable for the receiver or can be used as
a general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this
pin and can be programmed to generate an interrupt when a transition occurs. As an active-LOW
external sync input, it is used in COP mode to obtain character synchronization for the receiver
without receipt of a SYN character. This mode can be used in disc or tape controller applications or
for the optional byte timing lead in X.21.
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output:
Active-LOW. For half-duplex DMA operation, this output indicates to the DMA controller that one or
more characters are available in the receiver FIFO (when the receiver is enabled) or that the
indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this
pin is a general purpose output that can be asserted and negated under program control.
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-LOW. For full-duplex DMA operation, this output indicates to the DMA
controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA
asserted and negated under program control.
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-LOW. For half-duplex single address operation, this input indicates to the CDUSCC that the
receiver is enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For
full-duplex single address DMA operation, this input indicates to the CDUSCC that the DMA
controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning.
Because the state of this input can be read under program control, it can be used as a general
purpose input when not in single address DMA mode.
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-LOW. When
the channel is programmed for full-duplex single address DMA operation, this input is asserted to
indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load
transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program
6
NAME AND FUNCTION
2).
SC68C562
Product data