E28F008SA85 Intel, E28F008SA85 Datasheet - Page 16

• Manufacturer Part Number: E28F008SA85
• Manufacturer: Intel

Specifications of E28F008SA85

• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

28F008SA
At this point, a Read Array command can be written
to the CUI to read data from blocks other than that
which
commands at this time are Read Status Register
(70H) and Erase Resume (D0H), at which time the
WSM will continue with the erase process. The
erase suspend status and WSM status bits of the
status register will be automatically cleared and
RY/BY# will return to V
command
automatically outputs status register data when
read (see Figure 7 ; Erase Suspend/Resume
Flowchart ). V
28F008SA is in Erase Suspend.
4.7
Byte write is
sequence. The Byte Write Setup command (40H or
10H) is written to the CUI, followed by a second
write specifying the address and data (latched on
the rising edge of WE#) to be written. The WSM
then takes over, controlling the byte write and write
verify algorithms internally. After the two-command
byte write sequence is written to it, the 28F008SA
automatically outputs status register data when
read (see Figure 8; Automated Byte Write
Flowchart ). The CPU can detect the completion of
the byte write event by analyzing the output of the
RY/BY# pin, or the WSM status bit of the status
register. Only the Read Status Register command
is valid while byte write is active.
When byte write is complete, the byte write status
bit should be checked. If byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for “1”s that
do not successfully write to “0”s. The CUI remains
in read status register mode until further commands
are issued to it. If byte write is attempted while V
= V
write attempts while V
spurious results and should not be attempted.
5.0
Intel has designed extended cycling capability into
its
28F008SA is designed for 100,000 byte write/block
erase cycles on each of the sixteen 64-Kbyte
blocks. Low electric fields, advanced oxides and
minimal oxide area per cell subjected to the
16
PPL
ETOX
, the V
EXTENDED BLOCK
ERASE/BYTE WRITE CYCLING
is
Byte Write Setup/Write
Commands (40H or 10H)
suspended.
is
flash
PP
PP
written
must remain at V
executed by
status bit will be set to “1.” Byte
memory
PPL
OL
. After the Erase Resume
to
The
< V
it,
PP
technologies.
only
a two-command
< V
the
PPH
PPH
other
28F008SA
while the
produce
valid
The
PP
tunneling electric field combine to greatly reduce
oxide stress and the probability of failure. A 20-
Mbyte
28F008SAs has a MTBF (Mean Time Between
Failure) of 33.3 million hours
reliable than equivalent rotating disk technology.
6.0
The
programming algorithm of prior Intel Flash devices
on-chip, using the CUI, status register and WSM.
On-chip integration dramatically simplifies system
software and provides processor interface timings
to the CUI and status register. WSM operation,
internal verify and V
monitored and reported via the RY/BY# output and
appropriate
Automated Byte Write Flowchart , shows a system
software flowchart for device byte write. The entire
sequence is performed with V
abort occurs when RP# transitions to V
drops to V
data is partially written at the location where byte
write was aborted. Block erasure, or a repeat of
byte write, is required to initialize this data to a
known value.
7.0
As above, the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally,
including all preconditioning of block data. WSM
operation, erase success and V
presence are monitored and reported through
RY/BY# and the status register. Additionally, if a
command other than Erase Confirm is written to the
device following Erase Setup, both the Erase status
and Byte Write status bits will be set to “1”s. When
issuing the Erase Setup and Erase Confirm
commands, they should be written to an address
within the address range of the block to be erased.
Figure 6, Automated Block Erase Flowchart , shows
a system software flowchart for block erase.
1
(2000 files writes/erase) × (100,000 cycles per 28F008SA block) =
(200 × 10
Assumptions: 10-Kbyte file written every 10 minutes. (20-Mbyte
array)/(10-Kbyte file) = 2,000 file writes before erase required.
200 million file writes.
MTBF.
28F008SA
6
AUTOMATED BYTE WRITE
AUTOMATED BLOCK ERASE
solid-state
file writes) × (10 min/write) × (1 hr/60 min) = 33.3 × 10
PPL
status
. Although the WSM is halted, byte
integrates
PP
drive
register
high voltage presence are
PRELIMINARY
1
using
, over 600 times more
PP
at V
the
bits.
PP
PPH
an
high voltage
Quick-Pulse
. Byte write
Figure
IL
array
, or V
PP
of
8,
6