PCA9544D NXP Semiconductors, PCA9544D Datasheet - Page 5

• Manufacturer Part Number: PCA9544D
• Manufacturer: NXP Semiconductors

Specifications of PCA9544D

• Logical Function: I2C Multiplexer
• Configuration: 1 x 4:1
• Number Of Inputs: 4
• Number Of Outputs: 1
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Power Dissipation: 400mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9544 is
shown in Figure 4. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9544 which will be stored
in the Control Register. If multiple bytes are received by the
PCA9544, it will save the last byte received. This register can be
written and read via the I
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9544 has
been addressed. The 3 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, it will become active after a stop condition has been placed
on the I
HIGH state when the channel is made active, so that no false
conditions are generated at the time of connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
2004 Sep 29
INT3
X
X
X
X
X
0
4-channel I
2
INT2
INT3
C-bus. This ensures that all SCx/SDx lines will be in a
X
X
X
X
X
0
7
INTERRUPT BITS
INT2 INT1 INT0
(READ ONLY)
ENABLE BIT
INT1
6
1
X
X
X
X
X
0
1
FIXED
5
Figure 5. Control register
INT0
Figure 4. Slave address
2
X
X
X
X
X
0
1
4
C multiplexer with interrupt logic
2
C-bus.
0
3
X
D3
X
X
X
X
X
0
CHANNEL SELECTION BITS
A2
HARDWARE SELECTABLE
B2
2
B2
A1 A0
(READ/WRITE)
0
1
1
1
1
0
B1
1
B1
X
0
0
1
1
0
B0
0
R/W
B0
X
0
1
0
1
0
No channel
selected
Channel 0
enabled
Channel 1
enabled
Channel 2
enabled
Channel 3
enabled
No channel
selected;
power-up
default state
COMMAND
SW00386
SW00862
5
INTERRUPT HANDLING
The PCA9544 provides 4 interrupt inputs, one for each channel and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9544 and the interrupt output
will be driven LOW. The channel need not be active for detection of
the interrupt. A bit is also set in the control byte. Bits 4 – 7 of the
control byte correspond to channels 0 – 3 of the PCA9544,
respectively. Therefore, if an interrupt is generated by any device
connected to channel 2, the state of the interrupt inputs is loaded into
the control register when a read is accomplished. Likewise, an
interrupt on any device connected to channel 0 would cause bit 4 of
the control register to be set on the read. The master can then
address the PCA9544 and read the contents of the control byte to
determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544 to select this
channel, and locate the device generating the interrupt and clear it.
The interrupt clears when the device originating the interrupt clears.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to V
pull-up resistor.
Table 2. Control Register Read — Interrupt
NOTE: Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
POWER-ON RESET
When power is applied to V
the PCA9544 in a reset state until V
point, the reset condition is released and the PCA9544 registers and
I
causing all the channels to be deselected.
2
INT3
C state machine are initialized to their default states, all zeroes
X
X
X
X
X
X
0
1
INT2
X
X
X
X
X
X
0
1
INT1
X
X
0
1
X
X
X
X
INT0
X
X
X
X
X
X
0
1
DD
D3
X
X
X
X
X
X
X
X
, an internal Power On Reset holds
B2
DD
X
X
X
X
X
X
X
X
has reached V
B1
X
X
X
X
X
X
X
X
PCA9544
B0
X
X
X
X
X
X
X
X
Product data sheet
DD
POR
No interrupt
on channel 0
Interrupt on
channel 0
No interrupt
on channel 1
Interrupt on
channel 1
No interrupt
on channel 2
Interrupt on
channel 2
No interrupt
on channel 3
Interrupt on
channel 3
through a
COMMAND
. At this