STA333BW STMicroelectronics, STA333BW Datasheet - Page 28
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STA333BW
Manufacturer Part Number
STA333BW
Description
Manufacturer
STMicroelectronics
Datasheet
1.STA333BW.pdf
(67 pages)
Specifications of STA333BW
Operational Class
Class-AB
Audio Amplifier Output Configuration
1-Channel Mono/2-Channel Stereo
Audio Amplifier Function
Speaker
Total Harmonic Distortion
0.2@8Ohm@1W%
Single Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (typ)
3.3/5/9/12/15/18V
Power Supply Requirement
Quad
Rail/rail I/o Type
No
Power Supply Rejection Ratio
80dB
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
2.7/4.5V
Dual Supply Voltage (max)
3.6/21.5V
Operating Temp Range
-20C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
36
Package Type
PowerSSO EP
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STA333BW
Manufacturer:
ST
Quantity:
20 000
Part Number:
STA333BW13TR
Manufacturer:
ST
Quantity:
20 000
Part Number:
STA333BWJ13TR
Manufacturer:
ST
Quantity:
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Part Number:
STA333BWTR-9LF
Manufacturer:
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Quantity:
20 000
Register description
28/67
Different power devices use different output modes.
Table 22.
FFX compensating pulse size register
Table 23.
Table 24.
Overcurrent warning adjustment bypass
Table 25.
The OCRB is used to indicate how STA333BW behaves when an overcurrent warning
condition occurs. If OCRB = 0 and the overcurrent condition happens, the power control
block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to
eliminate the overcurrent warning condition. Once the overcurrent warning clipping
adjustment is applied, it remains in this state until reset is applied or OCRB is set to 1. The
level of adjustment can be changed via the TWOCL (thermal warning / overcurrent limit)
setting at address 0x37 of the user defined coefficient RAM
OCRB can be enabled when the output bridge is already on.
0
1
2
3
4
5
0000
0001
…
1111
7
Bit
Bit
Bit
CSZ[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFX power output mode
FFX compensating pulse size bits
Compensating pulse size
Overcurrent warning bypass
1
1
1
1
1
0
1
RST
RST
RST
0 ns (0 tick) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 tick) clock period compensating pulse size
OM0
OM1
CSZ0
CSZ1
CSZ2
CSZ3
OCRB
Doc ID 13773 Rev 3
Name
Name
Name
Compensating pulse size
Selects configuration of FFX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
When OM[1,0] = 11, this register determines the
size of the FFX compensating pulse from 0 clock
ticks to 15 clock periods.
0: overcurrent warning adjustment enabled
1: overcurrent warning adjustment disabled
(Section 6.7.7 on page
Description
Description
Description
STA333BW
54). The