PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet
PSB4860HV4.1
Specifications of PSB4860HV4.1
Available stocks
Related parts for PSB4860HV4.1
PSB4860HV4.1 Summary of contents
Page 1
ICs for Communications Sophisticated Answering Machine with Echo Cancellation SAM-EC PSB 4860 Version 4.1 Data Sheet 2000-01- ...
Page 2
PSB 4860 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies ...
Page 3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
SPS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Figure 1: Pin Configuration of PSB 4860 ...
Page 6
Figure 44: Memory Management - Structure of Voice Prompt Directory Figure 45: Audio File Organization - Example ...
Page 7
Figure 87: Analog Front End Interface ...
Page 8
Table 1: Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
Table 44: Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 45: ...
Page 10
Table 87: SSDI vs. IOM Table 88: IOM -2 Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
Overview General General Combined with an analog front end the provides a solution for embedded or stand alone answering machine applications. Together with a standard microcontroller for analog telephones these two chips form the core of a featurephone with ...
Page 12
Sophisticated Answering Machine with Echo Cancellation SAM Version 4.1 1.1 Features Digital Functions • High performance recording by DigiTape • Selectable compression rate (3.3, 5.6 or 10.3 kbit/s) • Variable playback speed • Support for DRAM/ARAM or Flash Memory (5V, ...
Page 13
Pin Configuration (top view ...
Page 14
Pin Definitions and Functions Table 1 Pin Definitions and Functions Pin No. Symbol P-MQFP-80 7, 15, 21 29, 39, 49, 58, 61, 67 DDA 4 V SSA 9, 16, 22 30, 40, ...
Page 15
Table 1 Pin Definitions and Functions 26 DD/DR 25 DU/DX 27 DXST 28 DRST SCLK 13 SDR 12 SDX 10 INT Data Sheet ® I/OD - IOM -2 Compatible Mode: Receive data from IOM I SSDI Mode: ...
Page 16
Table 1 Pin Definitions and Functions ...
Page 17
Table 1 Pin Definitions and Functions 33 VPRD/ FCLE 32 W/FWE 31 FRDY 5 OSC 1 6 OSC 2 8 CLK 2 XTAL 1 3 XTAL 2 37 SPS 0 38 SPS 41 ...
Page 18
Logic Symbol 1 RST AFECLK PSB AFEFS 4851 AFEDD AFEDU DDA - Figure 2 Logic Symbol of Data Sheet CLK OSC OSC XTAL 1 2 CAS / CAS / RAS/ ...
Page 19
Functional Block Diagram RST AFECLK Analog AFEFS Front End AFEDD Interface AFEDU MA -MA 0 Figure 3 Block Diagram of Data Sheet OSC OSC XTAL XTAL Reset and Timing Unit DSP Memory Interface MD -MD CAS ...
Page 20
System Integration The combined with an analog front end (PSB 4851) can be used in a variety of applications. This combination offers outstanding features like full duplex speakerphone and emergency operation. Some applications are given in the following sections. ...
Page 21
The PSB 4860 does not need to be directly connected to a Flash or DRAM but can use the SCI interface to store and get its data. An example is shown in Figure 5. tip/ ring line Figure 5 Stand-Alone ...
Page 22
Featurephone with Digital Answering Machine for ISDN Terminal Figure 6 shows an ISDN featurephone. All voice data is transferred by the IOM®-2 compatible interface. The is programmed by the SCI interface. The microcontroller can access the memory attached to ...
Page 23
DECT Basestation with Integrated Digital Answering Machine Figure 7 shows a DECT basestation based on the /PSB 4851 chipset. In this application it is possible to service both an external call and an internal call at the same time. ...
Page 24
Backward Compatibility The PSB 4860 Version 4.1 is backwards compatible with the PSB 4860 V2.1 and V3.1 with respect to: • Pin Configuration • Supply Voltage • Signal Levels • Start-up Sequence after Reset 1) • Register Definition All ...
Page 25
Functional Description Functional Units Functional Units The contains several functional units that can be combined with almost no restrictions to perform a given task. Figure 8 gives an overview of the important functional units. SSDI/IOM Channel ...
Page 26
Table 2 lists the available signals within the according to their reference points. Table 2 Signal Summary Signal Description S Silence 0 S Analog line input (channel 1 of PSB 4851 interface Analog ...
Page 27
The following figures show the connections for two typical states during operation. Units that are not needed are not shown. Inputs that are not needed are connected to S provides silence (denoted by 0). In figure 9 a hands-free phone ...
Page 28
In figure 10 a phone conversation using the speakerphone is in progress. One party is using the base station of a DECT system while the other party is using a mobile handset. At the same time an external call is ...
Page 29
Functional Units In this section the functional units of the are described in detail. The functional units can be individually enabled or disabled. 2.1.1 Full Duplex Speakerphone The speakerphone unit (figure 11) is attached to four signals (microphone, loudspeaker, ...
Page 30
The echo suppression unit attenuates the receive or transmit path dependent on what path is active. Without the echo cancellation unit and by using a high attenuation of the echo suppression unit, the echo suppression unit provides a half-duplex speakerphone. ...
Page 31
Table 3 Echo Cancellation Unit Registers Register # of Bits Name SAELEN 9 LEN SAEATT 15 ATT SAEGS 3 GS SAEPS1 3 PS SAEPS2 3 FB The length of the FIR filter can be varied from 127 to 511 taps ...
Page 32
Echo Suppression The echo suppression unit can be in one of three states: • transmit state • receive state • idle state In transmit state the microphone signal drives the line output while the line input is attenuated. In ...
Page 33
Figure 16 shows the signal flow graph of the echo suppression unit in more detail. microphone SDX SCAS loudspeaker Figure 16 Echo Suppression Unit - Signal Flow Graph The Attenuation Control performs the switching between the three possible states by ...
Page 34
Speech Detector For each signal source a speech detector (SDX, SDR) is available. The speech detectors are identical but can be programmed individually. Figure 17 shows the signal flow graph of a speech detector. LIM LP1 LIM Signal Preprocessing ...
Page 35
Therefore the output of the background noise monitor is a digital signal indicating speech (1) or noise (0). A small fade constant (LP2N) enables fast settling of LP2 to the average noise level after the end of ...
Page 36
Table 4 Speech Detector Parameters Parameter # of bytes Range LIM 1 OFF 1 PDS 1 PDN 1 LP1 1 LP2S 1 LP2N 1 LP2L 1 The input signal of the speech detector can be connected to either the input ...
Page 37
Speech Comparators (SC) The echo suppression unit has two identical speech comparators (SCAS, SCLS). Each comparator can be programmed individually to accommodate the different system characteristics of the acoustic interface and the line interface. As SCAS and SCLS are ...
Page 38
The main task of the comparator is to control the echo. The internal coupling due to the direct sound and mechanical resonances is covered by G. The external coupling, mainly caused by the acoustic feedback, is controlled by GD/PD. An ...
Page 39
GD* GD RX-Speech RX-noise Figure 20 Speech Comparator - Interdependence of Parameters According to figure 19, a compromise between the reserve GD and the decrement rate PD has to be made: a smaller reserve (GD) above the level enhancement ...
Page 40
Table 5 Speech Comparator Parameters Parameter # of bytes Range PDS 1 GDN 1 PDN 2.1.3.3 Attenuation Control The attenuation control unit performs state switching by controlling the attenuation stages GHX and GHR. In receive state, the ...
Page 41
Note: In addition, attenuation is also influenced by the Automatic Gain Control stages (AGCX, AGCR) in order to keep the total loop attenuation constant. Note: By programming parameter DS to 0xFF idle mode is disabled and the speakerphone will remain ...
Page 42
Example: COM = -30 dB AG_GAIN = 15 dB AG_ATT = 20 dB Figure 21 Echo Suppression Unit - Automatic Gain Control For reasons of physiological acceptance, the AGC gain is automatically reduced in case of continuous background noise (e.g. ...
Page 43
Table 8 Automatic Gain Control Parameters Parameter # of Bytes Range AG_INIT 1 - 95dB COM – AG_ATT -95 dB AG_GAIN AG_CUR 1 -95 dB ...
Page 44
Table 10 Speakerphone Control Registers SCTL 1 AGX SCTL 1 AGR SCTL 1 SDX SCTL 1 SDR AFECTL 4 ALS SSRC1 5 I1 SSRC1 5 I2 SSRC2 5 I3 SSRC2 5 I4 Data Sheet AGCX enable AGCR enable SDX input ...
Page 45
Line Echo Canceller The contains an adaptive line echo cancellation unit for the cancellation of near end echoes. The unit has three modes. Normal mode: The maximum echo length considered is 4 ms. This mode is always avail- able. ...
Page 46
Shadow FIR Filter I 2 Figure 23 Line Echo Cancellation Unit - Superior Mode with Shadow FIR The basic idea of the superior mode is shown in figure 23. The shadow FIR filter on the left hand side gets its ...
Page 47
Table 11 shows the registers associated with the line echo canceller. Table 11 Line Echo Cancellation Unit Registers Register # of Bits Name Comment LECCTL 1 EN LECCTL 1 MD LECCTL 1 CM LECCTL 1 AS LECCTL 5 I2 LECCTL ...
Page 48
DTMF Detector The contains an DTMF detector that recognizes the sixteen standard DTMF tones. Figure 24 shows a block diagram of the DTMF detector. The results of the detector are available in the status and a dedicated result register. ...
Page 49
CNG Detector The calling tone (CNG) detector can detect the standard calling tones of fax machines or modems. This helps to distinguish voice messages from data transfers. The result of the detector is available in the status register that ...
Page 50
Alert Tone Detector The alert tone detector can detect the standard alert tones (2130 Hz and 2750 Hz) for caller id protocols. The results of the detector are provided in the status register and register ATDCTL0. These registers can ...
Page 51
Universal Tone Detector The universal tone detector can be used instead of the CPT detector to detect special tones which are not covered by the standard CPT band-pass. Figure 27 shows the functional block diagram. A Programmable Band-pass I ...
Page 52
The conditions are met for 30ms, then violated for 3ms and then met again for 80 ms. In this case the break of 3ms is ignored, because it does not exceed the allowed break time TB1. Therefore the status bit ...
Page 53
CPT Detector The selected signal is monitored continuously for a call progress tone. The CPT detector consists of a band-pass and an optional timing checker (figure 28). Band-pass I 1 300-640 Hz Figure 28 CPT Detector - Block Diagram ...
Page 54
Table 22 CPT Detector Result Register # of Bits Name STATUS 1 CPT CPT is not affected by reading the status word automatically reset when the unit is disabled. Table 23 shows the control register for the CPT ...
Page 55
Caller ID Decoder The caller ID decoder is basically a 1200 baud modem (FSK, demodulation only). The bit stream is formatted by a subsequent UART and the data is available in a data register along with status information (figure ...
Page 56
Table 26 Caller ID Decoder Registers Register # of Bits Name CIDCTL0 8 DATA CIDCTL1 5 NMSS CIDCTL1 5 NMB CIDCTL1 6 MIN When the CID unit is enabled, it waits for a programmable number of continuous mark bits (CIDCTL1:NMB). ...
Page 57
Caller ID Sender The caller ID sender is a 1200 baud modem (FSK, modulation only). The byte data stream is formatted by a UART and then modulated (figure 31). SCI Figure 31 Caller ID Sender - Block Diagram The ...
Page 58
Table 29 Caller ID Sender Registers Register # of Bits Name CISDATA 8 DATA CISLEV 15 LEV CISSZR 15 SEIZ CISMRK 15 MARK Note: The caller ID sender cannot be activated at the same time as the caller ID decoder. ...
Page 59
DTMF Generator The DTMF generator can generate single or dual tones with programmable frequency and level. This unit is primarily used to generate the common DTMF tones but can also be used for signalling or other user defined tones. ...
Page 60
Speech Coder The speech coder (figure 33) has two input signals I the coder while the second signal (I recording. The signal I can be coded by either a 3.3 kbit/s, 5.6 kbit/s or 10.3 kbit/s coder ...
Page 61
The coder can optionally use silence gap coding. This feature can reduce the bit rate dramatically if there are long periods of silence in the incoming data stream. The GAP bit in the STATUS register is set when a gap ...
Page 62
The gap detector consists of a speech detector and a subsequent timer. A gap is detected whenever the speech detector detects no speech for at least time GAPT. The speech detector has the same signal flow graph and parameters as ...
Page 63
The task of the VOX detector is to distinguish between a signal containing voice and high energy signals called VOX containing just noise or periodic signals (e.g. sine waves). The general idea how to do this is to distinguish between ...
Page 64
CREST then the segment is also classified as low power. Otherwise the segment is classified as voice. Now the segments are combined into frames and for each frame the following calculation is ...
Page 65
The PSB 4860 offers the possibility to transfer the speech data via SCI. Then, no ARAM/ DRAM or Flash needs to be connected to the PSB 4860. To use this feature, the SCI bit in register SDCTL must be set. ...
Page 66
Speech Decoder The speech decoder (figure 35) decompresses the data previously coded by the speech coder unit and delivers a standard 128 kbit/s data stream. Memory Figure 35 Speech Decoder - Block Diagram The decoder supports fast (1.5 and ...
Page 67
Note: The last the file are not played back. Therefore an additional speech should be recorded. If tail-cut is used then it is recommended to cut 3 blocks (each block represents ...
Page 68
The PSB 4860 offers the possibility to transfer the speech data via SCI. To use this feature, the SCI bit in register SDCTL must be set. The speech decoder reads the speech data from register SDDATA. Bit DRQ in register ...
Page 69
Analog Front End Interface There are two identical interface channels to the analog frontend as shown in figure 36. The interface is described in chapter 2.4.3 and must be connected to the double codec PSB 4851. Channel 1 S ...
Page 70
Digital Interface There are two almost identical interfaces at the digital side (i.e., the SSDI/IOM interface described in chapters 2.4.1 and 2.4.2). As shown in figure 37, there are three channels available if the IOM SSDI mode Channel 1 ...
Page 71
Table 39 Digital Interface Registers Register # of Bits Name IFS4 5 I1 IFS4 5 I2 IFS4 5 I3 IFS4 1 HP IFS5 5 I1 IFS5 5 I2 IFS5 5 I3 IFS4 1 HP IFG5 8 ATT1 IFG5 8 ATT2 ...
Page 72
Universal Attenuator The contains an universal attenuator that can be connected to any signal (e.g. for side- tone gain in ISDN applications). Figure 38 Universal Attenuator - Block Diagram Table 40 shows the associated register. Table 40 Universal Attenuator ...
Page 73
Automatic Gain Control Unit In addition to the universal attenuator with programmable but fixed gain the contains an amplifier with automatic gain control (AGC). The AGC is preceded by a signal summation point for two input signals. One of ...
Page 74
Table 41 shows the associated registers. Table 41 Automatic Gain Control Registers Register # of Bits Name AGCCTL 1 EN AGCCTL 5 I1 AGCCTL 5 I2 AGCATT 15 ATT AGC1 8 AG_INIT AGC1 8 COM AGC2 8 SPEEDL AGC2 8 ...
Page 75
Equalizer The PSB 4860 also provides an equalizer that can be inserted into any signal path. The main application for the equalizer is the correction to the frequency characteristics of the microphone, transducer or loudspeaker. The equalizer consists of ...
Page 76
Due to the multitude of coefficients the PSB 4860 uses an indirect addressing scheme for reading or writing an individual coefficient. The address of the coefficient is given by ADR and the actual value is read or written to register ...
Page 77
Peak Detector The peak detector (figure 41) is usually not used in normal operation. It provides, however, an easy means to verify the minimum or maximum signal level of any signal S within the . The peak detector stores ...
Page 78
Data Sheet 78 PSB 4860 2000-01-14 ...
Page 79
Memory Management Memory Management Memory Management - General This section describes the memory management provided by the . As figure 42 shows, three units can access the external memory. During recording, the speech coder can write compressed speech data ...
Page 80
Figure 44 illustrates the basic structure of the voice prompt directory. directory Figure 44 Memory Management - Structure of Voice Prompt Directory The voice prompt directory contains 254 file descriptors. To each file descriptor a voice prompt file can be ...
Page 81
Figure 46 shows a binary file of 11 words containing a phonebook (with only two entries). Figure 46 Binary File Organization - Example The file 255 in the voice prompt area offers a convenient handling of phrases. The large number ...
Page 82
File commands are written to the FCMD register. The busy bit in the STATUS register is set within 150 µ (simultaneously with RDY). Some commands require additional parameters which have to be written into the specified registers prior ...
Page 83
A user data word consists of 12 bits that can be read or written by the user, one bit (R) that is reserved for future use and three read-only bits (D,M,E) which indicate the status of a file ...
Page 84
Table 47 Initialize Memory Parameters Register # of Bits Name FCTL 8 FNO CCTL 2 MT CCTL 1 MQ CCTL 1 MV CCTL 2 SFT CCTL 2 CDIV Table 48 Initialize Memory Results Register # of Bits Name FDATA 16 ...
Page 85
Table 49 Initialize Memory Parameters Register # of Bits Name FCMD 5 CMD FCMD 1 IN CCTL 2 MT CCTL 1 MQ CCTL 2 SFT CCTL 2 CDIV Possible Errors: • file open Note: This file command must be followed ...
Page 86
Table 51 Activate Memory Results Register # of Bits Name FDATA 16 FCTL 8 FNO Possible error conditions: • no memory connected • no directory found • device ID wrong (flash only) • corrupted files found (see FCTL:FNO) • directory ...
Page 87
Table 54 Read Data Results Register # of Bits Name FDATA 16 Possible error conditions: • file open • no activate performed • no prompt directory existing 2.2.3.5 Open File A specific file is opened for subsequent accesses with the ...
Page 88
Note: In case of Samsung and Toshiba Flash memory, existing ones in the entries RTC1/RTC2 of the file descriptor cannot be altered. Therefore TS should be set only once during the lifetime of a file. 2.2.3.6 Open Next Free File ...
Page 89
Seek The file pointer of the currently opened file is set to the position specified by FPTR. If the current file is the phrase file the starts the speech decoder immediately after the seek is finished (the bit SDCTL:EN ...
Page 90
Table 59 Cut File Parameters Register # of Bits Name FCMD 5 CMD FPTR 16 Possible error conditions: • file pointer out of range • voice prompt memory selected 2.2.3.9 Delete Multiple Files All files starting with the file number ...
Page 91
Table 61 Compress File Parameters Register # of Bits Name FCTL 8 FNO FPTR 16 Possible error conditions: • <fno> invalid • another file currently open • binary file selected Note: After power fail during execution of this command, the ...
Page 92
Note, that an aborted recompression command must be completed before a garbage collection can be performed. Table 64 Garbage Collection Parameters Register # of Bits Name FCMD 5 CMD FCMD 1 RD Possible error conditions: • ...
Page 93
Table 67 Access File Descriptor Results Register # of Bits Name FDATA 16 Possible error conditions: • file open for command Write File Descriptor - RTC1 / RTC2 • file not open for command Write File Descriptor - User Note: ...
Page 94
Table 70 Write Data Parameters Register # of Bits Name FCMD 5 CMD FDATA 16 Possible error conditions: • file pointer out of range (for existing files only) • voice prompt memory selected • memory full • audio file selected ...
Page 95
Low Level Memory Management Commands These commands allow the direct access of any location (single word) of the external memory. Additionally it is possible to erase any block in case of a Samsung or Toshiba Flash device. These commands ...
Page 96
Repeat 3) and 4) as often as necessary. The address is incremented automatically. Neglect BSY bit for these transfers but consider the RDY bit (no interrupt is issued). 7. Finish read access by transmitting 5F00 Possible error conditions: • ...
Page 97
Table 74 Block Erase Parameters Register # of Bits Name FCMD 5 CMD Possible error conditions: • file open • ARAM/DRAM configured Data Sheet Comment Block Erase command code 97 PSB 4860 2000-01-14 ...
Page 98
Execution Time The execution time of the file commands is determined by three factors: 1. Memory configuration 2. Memory state 3. Individual characteristics of the memory devices Therefore there is no general formula for an exact calculation of the ...
Page 99
Special Notes on File Commands 1. No MMU commands must be inserted between opening a file and writing data to it, either by writing data to a binary file or by enabling the coder for audio files. Therefore reading ...
Page 100
Data Sheet 100 PSB 4860 2000-01-14 ...
Page 101
Miscellaneous Miscellaneous Miscellaneous 2.3.1 Real Time Clock The supplies a real time clock which maintains time with a resolution of one second and a range one year. There are two registers which contain the current time ...
Page 102
Reset and Power Down Mode The can be in either reset mode, power down mode or active mode. During reset the clears the hardware configuration registers and stops both internal and external activity. The address lines MA -MA 0 ...
Page 103
Table 79 Interrupt Source Summary STATUS STATUS (old) (new) RDY=0 RDY=1 CIR=0 CIR=1 CIS=0 CIS=1 CIA=0 CIA=1 CD=0 CD=1 CD=1 CD=0 CPT/UTD=0 CPT/UTD=1 CPT or UT detected CPT/UTD=1 CPT/UTD=0 CPT or UT lost CNG=0 CNG=1 DTV=0 DTV=1 DTV=1 DTV=0 ATV=0 ...
Page 104
Abort If the cannot continue the current operations in progress (e.g. due to a transient loss of power) it stops operation and initializes all ...
Page 105
Table 81 Frame Synchronization Selection ACT MFS AFECLK 0 0 XTAL XTAL 2.3.9 Clock Tracking The can adjust AFECLK and AFEFSC dynamically to a slightly varying FSC. This mode requires that both AFEFSC and FSC ...
Page 106
Restrictions and Mutual Dependencies of Modules There are some restrictions concerning the modules that can be enabled at the same time. Table 82 and 83 summarize these restrictions. A checked cell indicates that the two modules (defined by the ...
Page 107
There are three classes of file commands denoted by the letters A, B and C. Table 84 shows the definitions of these classes: Table 84 File Command Classes Class Description A All commands B Background commands (Activate, Recompress, Garbage Collection, ...
Page 108
Table 85 Module Weights Module Digital Interface Digital Interface Digital Interface Analog Interface Clock Tracking Miscellaneous Alert Tone Detector Universal Tone Detector DTMF Detector Caller ID Sender Speech Coder + AGC + VOX detection + GAP coding Speech Decoder Example: ...
Page 109
Emergency Mode This mode is intended for a fast backup of controller data into non-volatile memory (flash memory) connected to the PSB 4860. In short, with this mode a maximum of 2048 bytes can be transferred with less than ...
Page 110
Procedure: 1. Preparation If a file command is currently running (except record, playback or phrase playback) then the file command must be aborted by setting the ICA bit of register FCMD. The file command will be aborted within 15 ms ...
Page 111
Interfaces Interfaces Interfaces This section describes the interfaces of the . The supports both an IOM single and double clock mode and a strobed serial data interface (SSDI). However, these two interfaces cannot be used simultaneously as they share ...
Page 112
Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However, programming is not supported via the monitor channels. DCL FSC * FSC ® Figure 50 IOM -2 Interface - Frame Start The supports both single clock ...
Page 113
T 1 DCL DU/DX DD/DR ® Figure 52 IOM -2 Interface - Double Clock Mode The supports up to three channels simultaneously for data transfer. If only two channels are used, then both the coding (PCM A-law, PCM µ -law ...
Page 114
Table 88 IOM -2 Interface Registers Register # of Bits Name SDCHN2 1 DD SDCHN2 1 PCM SDCHN2 1 PCD In A-law or µ -law mode, only 8 bits are transferred and therefore only one timeslot is needed for ...
Page 115
SSDI Interface The SSDI interface is intended for seamless connection to low-cost burst mode controllers (e.g. PMB 4725) and supports a single channel in each direction. The data stream is partitioned into frames. Within each frame, one 16 bit ...
Page 116
FSC DRST Figure 55 SSDI Interface - Active Pulse Selection Figure 56 shows the timing for the SSDI receiver. FSC DRST DCL DD/DR Figure 56 SSDI Interface - Receiver Timing Table 89 shows the registers used for configuration of the ...
Page 117
Analog Front End Interface The uses a four wire interface similar to the IOM with the analog front end (PSB 4851). The main difference is that all timeslots and the channel assignments are fixed as shown in figure 57. ...
Page 118
AFECLK AFEFS Figure 58 Analog Front End Interface - Frame Start Figure 58 shows the synchronization of a frame by AFEFS. The first clock of a new frame ( indicated by AFEFS switching from low to high before ...
Page 119
Serial Control Interface The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning ...
Page 120
CS SCLK SDR SDX INT c ,..,c : command word for status register read ,..,s : status register 15 0 Figure 60 Status Register Read Access CS SCLK SDR ...
Page 121
CS SCLK SDR SDX c ,..,c : command word for register write ,..,s : status register ,..,d : data to be written 15 0 Figure 62 Register Write Access CS ...
Page 122
CS SCLK SDR c ,..,c 15 Figure 64 Configuration Register Write Access or Register Read Command For all commands the external signal INT is deactivated as long as the chip is selected (CS is low). For a detailed discussion about ...
Page 123
In case of a configuration register read, R determines what pair of configuration registers read (table 95): Table 95 Address Field R for Configuration Register Read 9 Register pair 0 HWCONFIG 0 / HWCONFIG 1 1 HWCONFIG ...
Page 124
Data Sheet 124 PSB 4860 2000-01-14 ...
Page 125
Memory Interface The supports either Flash Memory or ARAM/DRAM as external memory for storing messages. If ARAM/DRAM is used, an EPROM can be added optionally to support read- only messages (e.g. voice prompts). Note: Although the memory accesses are ...
Page 126
PSB 4860 insofar as the control lines are released during reset and (optionally) power down. Instead of actively driving the lines FCS, FOE, FWE, FCLE and ALE these lines are pulled high by a weak pullup during reset ...
Page 127
ARAM/DRAM Interface The supports up to two banks of memory which may be 4 bit or 8 bit wide (Figure 65). If both banks are used, each one is connected identically with exception of the data lines D - ...
Page 128
Table 97 Address Line Usage (ARAM/DRAM Mode (2k refresh (4k refresh 16M x4 (4k refresh) 16M x4 (8k refresh (4k refresh (8k refresh) 1) see chip control register ...
Page 129
MCLK MA - RAS CAS ,CAS - Figure 67 ARAM/DRAM Interface - Write Cycle Timing MCLK RAS CAS ,CAS 0 1 Figure 68 ARAM/DRAM Interface - Refresh Cycle Timing The ensures that ...
Page 130
EPROM Interface The supports an EPROM in parallel with ARAM/DRAM. This interface is always 8 Bits wide and supports a maximum of 256 kBytes. Figure 69 shows a connection diagram and figure 70 shows the timing. This interface supports ...
Page 131
Parallel Flash Memory Interface The has special support for KM29N040, KM29W8000 and KM29N16000 or equivalent devices. Figure 71 shows the connection diagram for a single device. Figure 71 Parallel Flash Memory Interface - Connection Diagram No external components are ...
Page 132
Figure 72 shows an application with three KM29N040 devices - FOE FWR FRDY FCLE ALE Figure 72 Parallel Flash Memory Interface - Multiple Devices An ...
Page 133
The timing for the partial access cycles is shown in figures 73 to 74. Note that both FCS and MA -MA remain stable between the first and the last partial access of a device 0 15 access. MCLK* MA -MA ...
Page 134
MCLK* FWR MD - Figure 75 Parallel Flash Memory Interface - Data Write As there is no access that starts or stops with a data write cycle (figure 75) FCS is already low at the start of this ...
Page 135
Serial Flash Memory Interface The PSB 4860 can be connected four identical devices. It determines the number of connected devices automatically. The controller must provide the information on the type of the devices (Toshiba or Atmel). ...
Page 136
In each case multiple devices can be connected by sharing the lines MD SDI and MD /SDO as shown in figure 79. 2 PSB 4860 Figure 79 Serial Flash - Connection to Multiple TC ...
Page 137
Auxiliary Parallel Port The provides an auxiliary parallel port if the memory interface is in serial Flash or Samsung Flash mode. In this case the lines MA MA and are not needed for the memory interface ...
Page 138
Table 105 Multiplex Mode Registers Register # of bits Comment DOUT0 12 Output signals on MA DOUT1 12 Output signals on MA DOUT2 12 Output signals on MA DOUT3 12 Output signals (for pins configured as outputs) while MA DIN ...
Page 139
For each input pin the can be programmed to detect the following changes individually (table 106). Table 106 Interrupt Mask Definition for Parallel Port DMASK1 DMASK2 Prev. Value Cur. Value ...
Page 140
Data Sheet 140 PSB 4860 2000-01-14 ...
Page 141
Detailed Register Description The has a single status register (read only) and an array of data registers (read/write). The purpose of the status register is to inform the external microcontroller of important status changes of the and to provide ...
Page 142
CD Carrier Detect 0: No carrier detected 1: Carrier detected CIS Caller ID Stop Bits 0: The caller ID sender still sends data 1: The caller ID sender sends stop bits CPT Call Progress Tone 0: Currently no call progress ...
Page 143
New alert tone code available in ADCTL0 DA Data Available 0: No data available 1: Data of speech encoder to be fetched by microcontroller DRQ Data Request 0: No data requested 1: New data for speech decoder requested from ...
Page 144
Hardware Configuration Registers HWCONFIG 0 - Hardware Configuration Register ACS PPSDX Push/Pull for SDX 0: The SDX pin has open-drain characteristic 1: The SDX pin has push/pull characteristic PPINT Push/Pull for INT 0: The INT pin ...
Page 145
HWCONFIG 1 - Hardware Configuration Register 1 7 APP APP Auxiliary Parallel Port 7 6 Description 0 0 normal (ARAM/DRAM, Intel type flash, voice prompt EPROM APP static mode 1 0 APP multiplex mode 1 1 reserved ACT ...
Page 146
HWCONFIG 2 - Hardware Configuration Register 2 7 PPM ESDX ESDR PPM Push/Pull for Memory Interface (reset, power down) 0: The signals for the memory interface have push/pull characteristic 1: The signals for the memory interface have pullup/pulldown characteristic ESDX ...
Page 147
HWCONFIG 3 - Hardware Configuration Register LCM Low Clock Mode 0: normal XTAL frequency range 1: 15.368 MHz XTAL frequency SFI Serial Flash Interface 0: MD -MD are used for ARAM/DRAM or parallel flash interface 0 ...
Page 148
Read/Write Registers The following sections contains all read/write registers of the . The register addresses are given as hexadecimal values. Registers marked with an R are affected by reset or a wake up after power down. All other registers ...
Page 149
CPTMN CPT Minimum Times ..........................................................189 23h CPTMX CPT Maximum Times .........................................................190 24h CPTDT CPT Delta Times ................................................................191 25h R LECCTL Line Echo Cancellation Control ..........................................192 26h LECLEV Minimal Signal Level for Line Echo Cancellation ...............193 27h LECATT Externally Provided ...
Page 150
R DHOLD Data In Hold (Timeslot 3 or Static Mode) .......................... 234 53h SCVOX1 Vox Detector 1 ................................................................... 235 54h SCVOX2 Vox Detector 2 ................................................................... 236 55h SCVOX3 Vox Detector 3 ................................................................... 237 56h SCVOX4 Vox Detector 4 ................................................................... ...
Page 151
SAEGS Acoustic Echo Cancellation Global Scale ..........................277 83h SAEPS1 Acoustic Echo Cancellation Partial Scale ..........................278 84h SAEPS2 Acoustic Echo Cancellation First Block ..............................279 9Ah R CIDMF1 Caller ID Message Format .................................................280 9Bh R CIDMF2 Caller ID Message Format .................................................281 ...
Page 152
Table 107 Signal Encoding ...
Page 153
REV Revision The revision register can only be read. Note: A write access to the revision register does not change its content. It does, however, clear the ABT bit of the STATUS ...
Page 154
R CCTL Chip Control h 15 CDIV SFT CDIV Clock Division for Serial Flash Interface ( Description 0 0 XTAL XTAL: XTAL: XTAL:64 SFT Serial ...
Page 155
MQ Memory Quality 0: ARAM 1: DRAM MT Memory Type 3 2 Description 0 0 ARAM/DRAM 0 1 Serial flash memory 1 1 Samsung flash memory CS9 CAS selection 0: other memory 1: 256kx4 or 512kx8 memory SAS Split Address ...
Page 156
R INTM Interrupt Mask Register h 15 CIA RDY 1 GAP VOX CIR bit of this register is set to 0, the corresponding bit of the status register does not generate an ...
Page 157
R AFECTL Analog Front End Interface Control ALS Loudspeaker Amplification This value is transferred on channel C3 of the AFE interface. If the PSB 4851 is used it represents ...
Page 158
R IFS1 Interface Select The signal selection fields I1, I2 and I3 of IFS1 determine the outgoing signal of channel 1 of the analog interface. For the PSB 4851 this is usually ...
Page 159
R IFG1 Interface Gain IFG1 is associated with the incoming signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line in signal. IG1 In order to obtain ...
Page 160
R IFG2 Interface Gain IFG2 is associated with the outgoing signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line out signal. IG2 Gain of Amplifier IG2 ...
Page 161
R IFS2 Interface Select The signal selection fields I1, I2 and I3 of IFS2 determine the outgoing signal of channel 2 of the analog interface. For the PSB 4851 this is usually ...
Page 162
R IFG3 Interface Gain IFG3 is associated with the incoming signal of channel 2 of the analog interface. For the PSB 4851 this is usually the microphone signal. IG3 Gain of Amplifier IG3 In ...
Page 163
R IFG4 Interface Gain IFG4 is associated with the outgoing signal of channel 2 of the analog interface. For the PSB 4851 this is usually the loudspeaker signal. IG4 Gain of Amplifier IG4 In ...
Page 164
R SDCONF Serial Data Interface Configuration NTS Number of Timeslots ... ... ... DCL Double Clock Mode 0: Single Clock Mode ...
Page 165
R SDCHN1 Serial Data Interface Channel NAS NAS Number of active DRST strobe (SSDI interface mode ... ... ... PCD PCM Code 0: A-law ...
Page 166
Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case. Data Sheet Description ... ... ...
Page 167
R IFS3 Interface Select The signal selection fields I1, I2 and I3 of IFS3 determine the outgoing signal of channel 1 of the IOM/SSDI-interface. The HP bit enables a high-pass for the ...
Page 168
R SDCHN2 Serial Data Interface Channel Channel Split 0: Single 16 bit or single 8 bit channel 1: Two adjacent 8 bit channels (SDCHN2:PCM must ...
Page 169
R IFS4 Interface Select The signal selection fields I1, I2 and I3 of IFS4 determine the outgoing signal of ® channel 2 of the IOM -2/SSDI-interface. The HP bit enables a high-pass ...
Page 170
R IFG5 Interface Gain ATT1 255 (0 dB) ATT1 Attenuation for I3 (Channel 1) In order to obtain an attenuation A [dB channel 1 of the IOM (S ), the parameter ATT1 can ...
Page 171
R UA Universal Attenuator h 15 ATT 0 (-100 dB) ATT Attenuation for UA For a given attenuation A [dB] the parameter ATT can be calculated by the following formula: I1 Input Selection for UA Data Sheet 0 0 ...
Page 172
R DGCTL DTMF Generator Control Generator Enable 0: Disabled 1: Enabled MD Mode 0: raw 1: cooked DTC Dial Tone Code (cooked mode ...
Page 173
DGF1 DTMF Generator Frequency FRQ Frequency of Generator 1 The parameter FRQ for a given frequency f [Hz] can be calculated by the following formula: Data Sheet FRQ f × FRQ = 32768 ------------------ - ...
Page 174
DGF2 DTMF Generator Frequency FRQ Frequency of Generator 2 The parameter FRQ for a given frequency f [Hz] can be calculated by the following formula: Data Sheet FRQ f × FRQ = 32768 ------------------ - ...
Page 175
DGL DTMF Generator Level LEV2 LEV2 Signal Level of Generator 2 In order to obtain a signal level L (relative to the PCM maximum value) for generator 2 the value of LEV2 can be calculated according ...
Page 176
DGATT DTMF Generator Attenuation h 15 ATT2 ATT2 Attenuation of Signal S In order to obtain attenuation A the parameter ATT2 can be calculated by the formula: ATT2 ATT1 Attenuation of Signal S In order to obtain attenuation A ...
Page 177
R CNGCTL Calling Tone Control Enable 0: CNG unit disabled 1: CNG unit enabled I1 Input Selection for Calling Tone Detector Data Sheet ...
Page 178
CNGBT CNG Burst Time TIME Minimum Time for Calling Tone In order to obtain the parameter TIME for a minimum time t [ms] the following formula can be used: Data Sheet TIME ⁄ TIME = t ...
Page 179
CNGLEV CNG Minimal Signal Level MIN Minimum Signal Level for Calling Tone In order to obtain the parameter MIN for a minimum signal level L [dB] the following formula can be used: Data Sheet MIN ...
Page 180
CNGRES CNG Signal Resolution RES Signal Resolution The parameter RES depends on the noise level L [dB] as follows: Data Sheet RES ⁄ × 10 RES = – 4096 180 ...
Page 181
R ATDCTL0 Alert Tone Detection undefined EN Enable alert tone detection 0: The alert tone detection is disabled 1: The alert tone detection is enabled I1 Input signal selection ...
Page 182
ATDCTL1 Alert Tone Detection DEV 0 MD Alert tone detection mode 0: Only dual tones will be detected 1: Either dual or single tones will be detected DEV Maximum frequency deviation for alert ...
Page 183
R CIDCTL0 Caller ID Control DOT CID Enable 0: Disabled 1: Enabled DOT Drop Out Tolerance 0: Drop out during mark or seizure sequence aborts recognition 1: Drop out tolerance ...
Page 184
CIDCTL1 Caller ID Control NMB NMB Minimum Number of Mark Bits ... ... ... NMSS Minimum Number of Mark/Space Sequences 10 ...
Page 185
R IFS5 Interface Select The signal selection fields I1, I2 and I3 of IFS5 determine the outgoing signal of channel 3 of the IOM/SSDI-interface. The HP bit enables a high-pass for the ...
Page 186
R IFG6 Interface Gain ATT3 255 (0 dB) ATT3 Attenuation for I3 (Channel 3) In order to obtain an attenuation A [dB] the parameter ATT3 can be calculated by the following formula: Data Sheet 0 0 ...
Page 187
R CPTCTL Call Progress Tone Control CPT Detector Enable 0: Disabled 1: Enabled MD CPT Mode 0: raw 1: cooked I1 Input signal selection Data Sheet ...
Page 188
CPTTR Call Progress Tone Thresholds h 15 NUM 0 NUM Number of Cycles ... ... ... Minimal Signal-to-Noise Ratio ...
Page 189
CPTMN CPT Minimum Times h 15 MINB MINB Minimum Time for CPT Burst The parameter MINB for a minimal burst time TBmin [ms] can be calculated by the following formula: MING Minimum Time for CPT Gap The parameter MING ...
Page 190
CPTMX CPT Maximum Times h 15 MAXB MAXB Maximum Time for CPT Burst The parameter MAXB for a maximal burst time of TBmax [ms] can be calculated by the following formula: MAXG Maximum Time for CPT Gap The parameter ...
Page 191
CPTDT CPT Delta Times h 15 DIFB DIFB Maximum Time Difference between Consecutive Bursts The parameter DIFB for a maximal difference of t [ms] of two burst durations can be calculated by the following formula: DIFG Maximum Time Difference ...
Page 192
R LECCTL Line Echo Cancellation Control Enable 0: Disabled 1: Enabled MD Mode 0: Normal 1: Extended CM Compatibilitiy Mode 0: Standard Line Echo Canceller 1: ...
Page 193
LECLEV Minimal Signal Level for Line Echo Cancellation MIN The parameter MIN for a minimal signal level L (dB) can be calculated by the following formula: Data Sheet MIN × 512 96 ...
Page 194
LECATT Externally Provided Attenuation ATT The parameter ATT for an externally provided attenuation A (dB) can be calculated by the following formula: Note: ATT has a slightly different meaning in normal and in superior mode. In ...
Page 195
LECMGN Margin for Double Talk Detection MGN The parameter MGN for a margin of L (dB) can be calculated by the following formula: Note: MGM has a different meaning in normal and in superior mode. The ...
Page 196
R DDCTL DTMF Detector Control undefined EN Enable DTMF tone detection 0: The DTMF detection is disabled 1: The DTMF detection is enabled I1 Input signal selection DTC DTMF Tone ...
Page 197
DDTW DTMF Detector Signal Twist TWIST Signal twist for DTMF tone In order to obtain a minimal signal twist T the parameter TWIST can be calculated by the following formula: Note: TWIST must be in the ...
Page 198
DDLEV DTMF Detector Minimum Signal Level MIN Minimum Signal Level ... ... ... Note: Values outside the ...
Page 199
R FCFCTL Equalizer Control Enable equalizer 0: The equalizer is disabled 1: The equalizer is enabled ADR Coefficient address ...
Page 200
...