PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 119

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PSB4860HV4.1

Manufacturer Part Number
PSB4860HV4.1
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB4860HV4.1

Lead Free Status / Rohs Status
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Manufacturer
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Part Number:
PSB4860HV4.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
PSB 4860
2.4.4
Serial Control Interface
The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is
transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled by the at the rising edge of SCLK
and shifted out at the falling edge of SCLK. Each access must be terminated by a rising
edge of CS. The accesses to the can be divided into four classes:
1. Configuration Read/Write
2. Register Read/Write
3. Status/Data Read
4. Status/Data Read with Interrupt Acknowledge
If the is in power down mode, a read access to the status register does not deliver valid
data with the exception of the RDY bit (RDY=0). After the status has been read the
access can be either terminated or extended to read data from the . A register read/write
access can only be performed when the is ready. The RDY bit in the status register
provides this information.
Any access to the starts with the transfer of 16 bits to the over line SDR. This first word
specifies the access class, access type (read or write) and, if necessary, the register
accessed. Two access types terminate after the first word: configuration register write
and register read. If the configuration register is written, the first word also includes the
data and the access is terminated. After an access register read, an access of type data
read is necessary to obtain the register data. However, the data is valid only when
STATUS:RDY=1.
With a second word, all accesses beside configuration register write and register read
deliver the status register from the via line SDX. After the second word, the access
status register read terminates while all other accesses transfer data with a third word
and terminate then.
Figures 60 to 63 show the timing diagrams for the different access classes and types to
the .
Data Sheet
119
2000-01-14

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