PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 133

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The timing for the partial access cycles is shown in figures 73 to 74. Note that both FCS
and MA
access.
Figure 73 Parallel Flash Memory Interface - Command Write
Figure 74 Parallel Flash Memory Interface - Address Write
As there is no access that starts or stops with an address write cycle (figure 74) FCS is
already low at the start of this cycle and also remains low.
Data Sheet
0
-MA
MA
MD
MD
MCLK*
0
MCLK*
15
0
0
-MA
FCLE
-MD
-MD
FWR
FWR
FCS
ALE
remain stable between the first and the last partial access of a device
11
7
7
t
0
133
address latch cycle
t
1
data out
data out
t
2
t
3
PSB 4860
2000-01-14