GTL2005PW NXP Semiconductors, GTL2005PW Datasheet - Page 13

Translation - Voltage Levels 4-BIT BI-DIREC NON-LATCH TRAN

GTL2005PW

Manufacturer Part Number
GTL2005PW
Description
Translation - Voltage Levels 4-BIT BI-DIREC NON-LATCH TRAN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of GTL2005PW

Logic Type
Translator
Logic Family
GTL
Package / Case
SOT-402
Translation
GTL/GTL+ to LVTTL/TTL
High Level Output Current
- 12 mA
Low Level Output Current
40 mA
Propagation Delay Time
4.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / Rohs Status
 Details
Other names
GTL2005PW,112

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Manufacturer
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Quantity:
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NXP Semiconductors
13. Package outline
Fig 11. Package outline SOT402-1 (TSSOP14)
GTL2005_7
Product data sheet
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT402-1
max.
1.1
A
0.15
0.05
A
1
0.95
0.80
14
A
1
2
y
IEC
Z
0.25
pin 1 index
A
e
3
D
0.30
0.19
b
p
MO-153
JEDEC
0.2
0.1
c
b
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
p
8
7
REFERENCES
D
5.1
4.9
Rev. 07 — 3 February 2009
0
(1)
w
M
E
4.5
4.3
(2)
JEITA
scale
0.65
2.5
e
c
A
H
6.6
6.2
2
E
A
1
5 mm
L
1
0.75
0.50
L
H
p
E
E
detail X
0.4
0.3
Q
L
L
PROJECTION
EUROPEAN
p
0.2
v
Q
A
(A )
0.13
3
w
X
v
GTL2005
0.1
A
© NXP B.V. 2009. All rights reserved.
y
M
ISSUE DATE
A
99-12-27
03-02-18
0.72
0.38
Z
(1)
SOT402-1
8
0
o
o
13 of 19

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