SPD6729QCE Intel, SPD6729QCE Datasheet - Page 61
SPD6729QCE
Manufacturer Part Number
SPD6729QCE
Description
PCI To PC Card (PCMCIA) Controller 208-Pin MQFP
Manufacturer
Intel
Datasheet
1.SPD6729QCE.pdf
(116 pages)
Specifications of SPD6729QCE
Package
208MQFP
Operating Temperature
0 to 70 °C
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8.2
Datasheet
Register Name: System I/O Map 0-1 Start Address Low
Index: 08h, 0Ch
Bit 7
Bit 4: I/O Window 1 Size
When bit 5 of this register is a ‘0’, this bit determines the width of the data path for I/O Window 1
accesses to the card. When bit 5 is a ‘1’, this bit is ignored.
Bit 5: Auto-Size I/O Window 1
This bit controls the method that the width of the data path for I/O Window 1 accesses to the card is
determined. Note that when this bit is a ‘1’, the -IOIS16 signal (
the data path to the card. This bit must be set to a ‘1’ for correct ATA mode operation (see
Mode Operation” on page
Bit 7: Timing Register Select 1
This bit determines the access timing specification (see
Window 1.
System I/O Map 0-1 Start Address Low
There are two separate System I/O Map Start Address Low registers, each with identical fields.
These registers are located at the following indexes:
Bit 6
0
1
0
1
0
1
Index
08h
0Ch
8-bit data path to I/O Window 1.
16-bit data path to I/O Window 1.
I/O Window 1 Size (see bit 4 of this register) determines the data path for I/O Window 1
accesses.
The data path to I/O Window 1 will be determined based on -IOIS16 returned by the card.
Accesses made with timing specified in Timer Set 0.
Accesses made with timing specified in Timer Set 1.
Bit 5
(Socket A)System I/O Map Start Address Low
System I/O Map 0 Start Address Low
System I/O Map 1 Start Address Low
91).
Bit 4
Start Address 7-0
RW:00000000
PCI-to-PC Card (PCMCIA) Controller — PD6729
Bit 3
“Timing Registers” on page
Bit 2
Table
Register Compatibility Type: 365
2) determines the width of
Bit 1
Register Per: socket
87) for I/O
Bit 0
“ATA
61
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