ST70235A STMicroelectronics, ST70235A Datasheet
ST70235A
Specifications of ST70235A
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ST70235A Summary of contents
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... ANSI T1.413 "Issue 2" DMT ADSL specification. The chip supports UTOPIA level 1 and UTOPIA level 2 interface. The ST70235A can be split up into two different sections. DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for ...
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... ST70235A Figure 1 : Block Diagram TEST SIGNALS TEST MODULE DSP AFE INTERFACE FRONT-END AFE CONTROL AFE INTERFACE CONTROL Transient Energy Capabilities ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of the device are to be able to withstand minimum 2000V for the HBM and minimum 250V for CDM ...
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... OBC_TYPE 33 INTB 34 RESETB 35 VSS 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 ST70235A ST70235A 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 ...
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... ST70235A PIN FUNCTIONS Pin Name 1 VSS 2 AD_0 3 AD_1 4 AD_2 5 VDD 3.3 6 AD_3 7 AD_4 8 VSS 9 AD_5 10 AD_6 11 VDD 3.3 12 AD_7 13 AD_8 14 AD_9 15 VSS 16 AD_10 17 AD_11 18 VDD 1.8 19 AD_12 20 VSS 21 PCLK 22 VDD 3.3 23 AD_13 24 AD_14 25 AD_15 26 VSS 27 BE1 28 ALE 29 VDD 3.3 30 CSB 31 WR_RDB ...
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... Utopia RX Start of Cell Utopia RX Cell Available Utopia RX Enable 0V Ground Utopia TX Clock Utopia TX Start of Cell Utopia TX Cell Available Utopia TX Enable (VSS + 3.3V) Power Supply 0V Ground Utopia TX Data 7 Utopia TX Data 6 (VSS + 3.3V) Power Supply Utopia TX Data 5 Utopia TX Data 4 Utopia TX Data 3 Utopia TX Data 2 ST70235A 5/28 ...
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... ST70235A PIN FUNCTIONS (continued) Pin Name 81 VDD 1.8 82 U_TxData_1 83 U_TxData_0 84 U_TxADDR_4 85 U_TxADDR_3 86 VDD 1.8 87 U_TxADDR_2 88 U_TxADDR_1 89 U_TxADDR_0 90 RESERVED 91 VSS 92 RESERVED 93 RESERVED 94 RESERVED 95 VDD 3.3 96 RESERVED 97 RESERVED 98 RESERVED 99 RESERVED 100 RESERVED 101 RESERVED 102 VSS 103 RESERVED 104 RESERVED 105 RESERVED 106 ...
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... Compensation Cell Resistor (see note 1) 0V Ground Disable Compensation Cell (see note 1) Reserved (VSS + 1.8V) Power Supply Test pin, active high Transmit data nibble Transmit data nibble 0V Ground Transmit data nibble Transmit data nibble (VSS + 3.3V) Power Supply resistor on board. ST70235A 7/28 ...
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... ST70235A PIN SUMMARY Mnemonic Type BS Type Power Supply VDD 3.3 VDD 1.8 VSS ATC INTERFACE ALE I PCLK I CSB I BE1 I WR_RDB I RDYB OZ INTB OBC_TYPE I-PD TEST ACCESS PART INTERFACE TDI I-PU TDO OZ TCK I-PD TMS I-PU TRSTB I-PD ANALOG FRONT END INTERFACE ...
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... After the first stage time domain equalization and FFT block an ICI (InterCarrier Interference) free information stream turns out. Function reduce the effect of transmit direction, the DSP Front-End sidelobe filtering, clipping, ST70235A Inter-Symbol delay 9/28 ...
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... ST70235A Figure 3 : DSP Front-End Receive From Analog Front-end Figure 4 : DSP Front-End Transmit FILTERING From CLIPPING DMT DELAY Modem EQUALIZER Figure 5 : DMT Modem (Rx & Tx) To/From FFT DSP FE IFFT FEQ COEFFICIENTS This stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase ...
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... These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module. ST70235A is used to AOC 11/28 ...
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... ST70235A Figure 6 : Generic TC Layer Functions To/From Demapper DATA PATX MERGER INTERLEAVER DE-INTERLEAVER ATM Specific TC Layer Functions The 2 bytes streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell Header Error Correction (HEC) and detection ...
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... WRB RDYB 1: RDB = WR_RDB is high. Data and addresses are multiplexed ST70235A works in 16 bits data access, so address bit 0 is not used. Address bit 1 is not multiplexed with data. It has its own pin : BE1. Byte access are not supported. Access cycle read ...
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... ST70235A Figure 11 : Generic Processor Interface Read Timing Cycle MClk ALE CSB Address/DATA 1 RDB RDYB 1: WRB = BE1 is high. Generic processor interface Cycle Timing All AC characteristics are indicated for a 100pF capacitive load.Cycle timing for generic interface. Table 2 : Cycle timing Symbol Tcsre Access Time ...
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... Utopia Level 1 – Utopia Level 2 The interface selection is programmed by writing the Utopia PHY address register. Only one interface can be enabled in a ST70235A configuration. Utopia Level 1 supports only one PHY device. Utopia Level 2 supports multi-PHY devices (See Utopia Level 2 specifications). ...
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... Note 1. Active low signal When RxEnb is asserted, the ST70235A reads data from its internal fifo and presents it on RxData and RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on the rising edge of RxSOC on the rising edge of RxClk. ...
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... Transmit Data (8bits) TxSOC I Transmit Start of Cell 1 I Reference Clock TxRef Note 1. Active low signal The ST70235A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC Electrical Characteristics Symbol F Clock frequency Tc Clock duty cycle Tj Clock peak to peak jitter Trf ...
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... ST70235A RxAddr, RxEnb, AC Electrical Characteristics Symbol T5 Input setup time to RxClk T6 Hold time to RxClk L Load Figure 15 : Timing (Utopia 2 Transmit Interface) Polling TxClk TxAddr 1F N TxClav N+1 N TxEnb* P45 P46 P47 P48 TxData TxSOC Cell transmission from: PHY N Figure 16 : Timing Specification (Utopia 2) Clock ...
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... TxClav and 1 RxClav". PHY Device Identification The ST70235A holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields in the Utopia PHY address register ...
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... ST70235A Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Utopia interface enabled by the TRI_STATE_EN bit in the Rx_interface control register. Pin Description Utopia 2 (Receive Interface) Name Type Meaning RxClav O Receive Cell available RxEnb* I Receive Enable ...
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... Figure 19 : Receive Word Timing Diagram MCLK CLWD AFRXD Cycle0 GP_IN(0) Test0 The ST70235A fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals result 4 cycles are needed to transfer 1 word. ...
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... ST70235A Figure 20 : Transmit Interface MCLK Tv AFTXD Figure 21 : Receive Interface MCLK Ts Th AFRXD Tc CLWD Table 5 : Master Clock (MCLK) AC Electrical Characteristics Symbol Parameter F Clock Frequency Tper Clock Period Th Clock Duty Cycle Table 6 : AFTXD, AFTXED, CLWD AC Electrical Characteristics Symbol Parameter Tv Data Valid Time Tc Data Valid Time ...
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... U_Rxdata[7] U_Rxaddr[0] B U_Rxaddr[1] B U_Rxaddr[2] B U_Rxaddr[3] B U_Rxaddr[4] B Gp_In[0] B Gp_In[1] B U_Rxrefb B U_Txrefb B U_Rxclk B U_Rxsoc B U_Rxclav B U_Rxenb B U_Txclk C U_Txsoc B U_Txclav B U_Txenb B U_Txdata[7] I U_Txdata[6] C ST70235A Sequence BS Number Type IO30 I IO31 I IO32 B IO33 I IO34 O IO35 I IO38 B IO39 B IO41 B IO42 B IO44 B IO45 B IO47 B IO48 B IO50 I IO51 I IO52 I ...
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... Bits from are reserved I Reset Initialization I The ST70235A supports two reset modes – A 'hardware' reset is activated by the RESETB pin (active low). A hard reset occurs when a low O input value is detected at the RESETB input. NONE The low level must be applied for at least 1ms to guarantee a correct reset operation ...
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... SS Test Condition pull up /pull down pull up /pull down Test Condition Slow edge < 1V XmA* OUT I = XmA* OUT Minimum Typical Maximum - -15 -66 -125 15 66 125 50 50 Minimum Typical Maximum 0.8 2.0 0.4 0.7 0.4 2.4 ST70235A Unit Unit 25/28 ...
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... ST70235A TQFP144 PACKAGE MECHANICAL DATA Figure 22 : Package Outline TQFP144 144 Dimension Minimum A A1 0.05 A2 1.35 B 0. 26/28 e 109 108 Millimeter Typical Maximum 1.60 0.15 1.40 1.45 0.22 0.27 0.20 22.00 20.00 17.50 0.50 22.00 20.00 17.50 0.60 0.75 1.00 0° (minimum), 7° (maximum) ...
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... ST70235A 27/28 ...
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... ST70235A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...