ST70235A STMicroelectronics, ST70235A Datasheet - Page 23

• Manufacturer Part Number: ST70235A
• Description: Transceiver 144-Pin TQFP
• Manufacturer: STMicroelectronics

Specifications of ST70235A

• Package: 144TQFP
• Power Supply Type: Analog
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62|3 V
• Maximum Operating Supply Voltage: 1.98|3.6 V
• Case: QFP

Tests, Clock, JTAG Interface
– Mclk: Master Clock (35.328MHz) generated by
– ATM receive interface, asynchronous clock gen-
– ATM transmit interface, asynchronous clock
– ATC clock (Pclk): external asynchronous clock
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing. This JTAG TAP interface consists in 5
signals:
TDI, TDO, TCK & TMS.
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
Table 8 : Boundary Scan Chain Sequence
VCXO
erated by Utopia Master
generated by Utopia Master
(synchronous with ATC in case of i960 specific
interface)
Signal
Ad[10]
Ad[11]
Ad[12]
Ad[13]
Ad[14]
Ad[15]
Name
Ad[0]
Ad[1]
Ad[2]
Ad[3]
Ad[4]
Ad[5]
Ad[6]
Ad[7]
Ad[8]
Ad[9]
Pclk
Be1
Ale
Sequence
Number
IO10
IO12
IO13
IO14
IO16
IO17
IO19
IO21
IO23
IO24
IO25
IO27
IO28
IO2
IO3
IO4
IO6
IO7
IO9
Type
BS
C
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
I
Table 8 : Boundary Scan Chain Sequence
U_Rxdata[0]
U_Rxdata[1]
U_Rxdata[2]
U_Rxdata[3]
U_Rxdata[4]
U_Rxdata[5]
U_Rxdata[6]
U_Rxdata[7]
U_Rxaddr[0]
U_Rxaddr[1]
U_Rxaddr[2]
U_Rxaddr[3]
U_Rxaddr[4]
U_Txdata[7]
U_Txdata[6]
Obc_Type
U_Rxclav
U_Rxrefb
U_Rxenb
U_Txclav
U_Txrefb
U_Rxsoc
U_Txenb
U_Txsoc
Gp_In[0]
Gp_In[1]
Wr_Rdb
U_Rxclk
U_Txclk
Resetb
Signal
Name
Rdyb
Csb
Intb
Sequence
Number
IO30
IO31
IO32
IO33
IO34
IO35
IO38
IO39
IO41
IO42
IO44
IO45
IO47
IO48
IO50
IO51
IO52
IO53
IO55
IO56
IO58
IO60
IO61
IO63
IO64
IO65
IO66
IO68
IO69
IO70
IO71
IO74
IO75
ST70235A
Type
BS
O
O
C
O
C
O
B
B
B
B
B
B
B
B
B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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