CY7C1347F-133AI Cypress Semiconductor Corp, CY7C1347F-133AI Datasheet - Page 10

• Manufacturer Part Number: CY7C1347F-133AI
• Description: SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347F-133AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4.5 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Switching Characteristics
Document #: 38-05213 Rev. *D
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
12. t
13. At any given voltage and temperature, t
14. This parameter is sampled and not 100% tested.
15. Timing references level is 1.5V when V
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
11. This part has a voltage regulator internally; t
POWER
CYC
CH
CL
AS
AH
CO
DOH
WES
WEH
ALS
ALH
DS
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
V
read or write
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-up Before CLK
Rise
Address Hold After CLK Rise
Data Output Valid After CLK
Rise
Data Output Hold After CLK
Rise
GW, BWS
CLK Rise
GW, BWS
Rise
ADV/LD Set-up Before CLK
Rise
ADV/LD Hold after CLK Rise
Data Input Set-up Before CLK
Rise
Data Input Hold After CLK
Rise
Chip Enable Set-up Before
CLK Rise
Chip Enable Hold After CLK
Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output
High-Z
OE LOW to Output
Low-Z
OE LOW to Output Valid
DD
, and t
(min.) to the first access
[12, 13, 14]
[12, 13, 14]
OEHZ
Description
[3:0]
[3:0]
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[11]
Set-up Before
Hold After CLK
[12, 13, 14]
[12, 13, 14]
DDQ
OEHZ
Over the Operating Range
POWER
= 3.3V and is 1.25V when V
is less than t
is the time that the power needs to be supplied above V
Min.
4.0
1.7
1.7
0.8
0.4
1.0
0.8
0.4
0.8
0.4
0.8
0.4
0.8
0.4
1
0
0
OELZ
-250
Max.
and t
2.6
2.6
2.6
2.6
CHZ
DDQ
is less than t
Min.
4.4
2.0
2.0
1.2
0.5
1.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
[15, 16]
1
0
0
= 2.5V on all data sheets.
-225
Max.
2.6
2.6
2.6
2.6
CLZ
to eliminate bus contention between SRAMs when sharing the same
Min.
5.0
2.0
2.0
1.2
0.5
1.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
1
0
0
-200
Max.
2.8
2.8
2.8
2.8
DD
(minimum) initially before a read or write operation
Min.
6.0
2.5
2.5
1.5
0.5
2.0
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1
0
0
-166
Max.
3.5
3.5
3.5
3.5
Min.
CY7C1347F
7.5
3.0
3.0
1.5
0.5
2.0
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1
0
0
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Max.
4.0
4.0
4.0
4.5
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns